DS92LV16 Datasheet, PDF (4/25 Pages) National Semiconductor (TI) – 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

DS92LV16
SNLS138H – JANUARY 2001 – REVISED APRIL 2013
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SERIALIZER TIMING REQUIREMENTS FOR TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
t_TCP
t_TCIH
t_TCIL
t_CLKT
t_JIT
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition Time
TCLK Input Jitter
12.5
0.4T
0.4T
T
0.5T
0.5T
3
40
0.6T
0.6T
6
80
SERIALIZER SWITCHING CHARACTERISTICS
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
t_LLHT
Bus LVDS Low-to-High
Transition Time
R_L = 100Ω
0.2
See Figure 4
t_LHLT
Bus LVDS High-to-Low
Transition Time
C_L=10pF to GND
0.2
t_DIS
DIN (0-15) Setup to TCLK R_L = 100Ω
t_DIH
DIN (0-15) Hold from TCLK
See Figure 7
C_L=10pF to GND
t_HZD
DO ± HIGH to
TRI-STATE Delay
2.4
0
2.3
t_LZD
DO ± LOW to
TRI-STATE Delay
R_L = 100Ω
See Figure 8⁽¹⁾
1.9
t_ZHD
DO ± TRI-STATE to
HIGH Delay
C_L=10pF to GND
1.0
t_ZLD
DO ± TRI-STATE to
LOW Delay
1.0
t_SPW
t_PLD
t_SD
SYNC Pulse Width
Serializer PLL Lock Time
Serializer Delay
R_L = 100Ω
See Figure 9
R_L = 100Ω
See Figure 10
5*t_TCP
510*t_TCP
t_TCP + 1.0
t_TCP + 2.0
t_RJIT
Random Jitter
t_DJIT
Deterministic Jitter
35 MHz
See Figure 16
80 MHz
10
-240
-75
Max
0.4
0.4
10
10
10
10
6*t_TCP
513*t_TCP
t_TCP + 4.0
140
100
(1) Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
DESERIALIZER TIMING REQUIREMENTS FOR REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
t_RFCP
t_RFDC
t_RFCP / t_TCP
t_RFTT
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to TCLK
REFCLK Transition Time
12.5
T
40
40
50
60
0.95
1.05
6
Units
ns
ns
ns
ns
ps (rms)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps (rms)
ps
ps
Units
ns
%
ns
4
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