DS92LV16 Datasheet, PDF (14/25 Pages) National Semiconductor (TI) – 16-Bit Bus LVDS Serializer/Deserializer - 25 - 80 MHz

DS92LV16
SNLS138H – JANUARY 2001 – REVISED APRIL 2013
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LOOPBACK TEST OPERATION
The DS92LV16 includes two Loopback modes for testing the device functionality and the transmission line
continuity. Asserting the Line Loopback control signal connects the serial data input (RIN+/−) to the serial data
output (DO+/−) and to the parallel data output (ROUT[0:15]). The serial data goes through deserializer and
serializer blocks.
Asserting the Local Loopback control signal connects the parallel data input (DIN[0:15]) back to the parallel data
output (ROUT[0:15]). The connection route includes all the functional blocks of the SER/DES Pair. The serial
data output (DO+/−) is automatically disabled during the Local Loopback operating mode.
TRI-STATE
When the system drives the REN pin low, the Deserializer output enter TRI-STATE. This will TRI-STATE the
receiver output pins (ROUT[0:15]) and RCLK. When the system drives REN high, the Deserilaizer will return to
the previous state as long as all other control pins remain static (RPWDN*).
When the system drives the DEN pin low, the Serializer output enters TRI-STATE. This will TRI-STATE the
LVDS output. When the system drives the DEN signal high, the Serializer output will return to the previous state
as long as all other control and data input pins remain in the same condition as when the DEN was driven low.
APPLICATION INFORMATION
Using the DS92LV16
The DS92LV16 combines a Serializer and a Deserializer into a single chip that sends 16 bits of parallel TTL data
over a serial Bus LVDS link up to 1.28 Gbps. Serialization of the input data is accomplished using an onboard
PLL at the Serializer which embeds two clock bits with the data. The Deserializer uses a separate reference
clock (REFCLK) and an onboard PLL to extract the clock information from the incoming data stream and
deserialize the data. The Deserializer monitors the incoming clock information to determine lock status and will
indicate loss of lock by raising the LOCK output.
Power Considerations
All CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally, the
constant current source nature of the LVDS outputs minimize the slope of the speed vs. I_CC curve of CMOS
designs.
Powering Up the Deserializer
The REFCLK input can be running before the Deserializer is powered up and it must be running in order for the
Deserializer to lock to incoming data. The Deserializer outputs will remain in TRI-STATE until the Deserializer
detects data transmission at its inputs and locks to the incoming stream.
Noise Margin
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic factors include:
• Serializer: TCLK jitter, V_CC noise (noise bandwidth and out-of-band noise)
• Media: ISI, V_CM noise
• Deserializer: V_CC noise
For typical receiver noise margin, please see Figure 17.
Recovering from LOCK Loss
In the case where the Serializer loses lock during data transmission up to 5 cycles of data that was previously
received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that
invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been
lost it is possible that data was also lost during these cycles. When the Deserializer LOCK pin goes low, data
from at least the previous 5 cycles should be resent upon regaining lock.
Lock can be regained at the Deserializer by causing the Serializer to resend SYNC patterns as described above
or by random lock which can take more time depending upon the data patterns being received.
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