DRV8412_15 Datasheet, PDF (5/42 Pages) Texas Instruments – DRV84x2 Dual Full-Bridge PWM Motor Driver

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NAME
OUT_D
PVDD_A
PVDD_B
PVDD_C
PVDD_D
PWM_A
PWM_B
PWM_C
PWM_D
RESET_AB
RESET_CD
FAULT
VDD
VREG
THERMAL PAD
HEAT SLUG
PIN
DRV8412
39
26, 27
32
35
40, 41
17
15
7
5
16
6
18
2
11
—
N/A
DRV8432
22
34
29
26
21
4
6
14
16
5
15
3
17
10
N/A
—
DRV8412, DRV8432
SLES242G – DECEMBER 2009 – REVISED DECEMBER 2014
Pin Functions (continued)
I/O TYPE ⁽¹⁾
DESCRIPTION
O
Output, half-bridge D
P
Power supply input for half-bridge A requires close decoupling capacitor to ground.
P
Power supply input for half-bridge B requires close decoupling capacitor to gound.
P
Power supply input for half-bridge C requires close decoupling capacitor to ground.
P
Power supply input for half-bridge D requires close decoupling capacitor to ground.
I
Input signal for half-bridge A
I
Input signal for half-bridge B
I
Input signal for half-bridge C
I
Input signal for half-bridge D
I
Reset signal for half-bridge A and half-bridge B, active-low
I
Reset signal for half-bridge C and half-bridge D, active-low
O
Fault signal, open-drain, active-low. An internal pullup resistor to VREG (3.3 V) is
provided on output. Level compliance for 5-V logic can be obtained by adding
external pullup resistor to 5 V
P
Power supply for digital voltage regulator requires capacitor to ground for
decoupling.
P
Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
T
Solder the exposed thermal pad to the landing pad on the pcb. Connect landing
pad to bottom side of pcb through via for better thermal dissipation. This pad should
be connected to GND.
T
Mount heat sink with thermal interface on top of the heat slug for best thermal
performance.
MODE PINS
M3
M2
M1
0
0
0
0
0
1
0
1
0
0
1
1
1
x
x
Mode Selection Pins
OUTPUT
CONFIGURATION
DESCRIPTION
2 FB or 4 HB
2 FB or 4 HB
1 PFB
2 FB
Reserved
Dual full bridges (two PWM inputs each full bridge) or four half bridges with
cycle-by-cycle current limit
Dual full bridges (two PWM inputs each full bridge) or four half bridges with
OC latching shutdown (no cycle-by-cycle current limit)
Parallel full bridge with cycle-by-cycle current limit
Dual full bridges (one PWM input each full bridge with complementary PWM
on second half bridge) with cycle-by-cycle current limit
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Product Folder Links: DRV8412 DRV8432
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