DRV8412_15 Datasheet, PDF (4/42 Pages) Texas Instruments – DRV84x2 Dual Full-Bridge PWM Motor Driver

DRV8412, DRV8432
SLES242G – DECEMBER 2009 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
DRV8412
DDW Package
(Top View)
GVDD_C
1
VDD
2
NC
3
NC
4
PWM_D
5
RESET_CD
6
PWM_C
7
M1
8
M2
9
M3
10
VREG
11
AGND
12
GND
13
OC_ADJ
14
PWM_B
15
RESET_AB
16
PWM_A
17
FAULT
18
NC
19
NC
20
OTW
21
GVDD_B
22
44
GVDD_D
43
BST_D
42
NC
41
PVDD_D
GVDD_B
1
40
PVDD_D
OTW
2
39
OUT_D
FAULT
3
38
GND_D
PWM_A
4
37
GND_C
RESET_AB
5
36
OUT_C
PWM_B
6
35
PVDD_C
OC_ADJ
7
34
BST_C
GND
8
33
BST_B
32
PVDD_B
AGND
9
31
OUT_B
30
GND_B
VREG
10
M3
11
29
GND_A
M2
12
28
OUT_A
M1
13
27
PVDD_A
PWM_C
14
26
PVDD_A
RESET_CD
15
25
NC
PWM_D
16
24
BST_A
VDD
17
23
GVDD_A
GVDD_C
18
DRV8432
DKD Package
(Top View)
www.ti.com
36
GVDD_A
35
BST_A
34
PVDD_A
33
OUT_A
32
GND_A
31
GND_B
30
OUT_B
29
PVDD_B
28
BST_B
27
BST_C
26
PVDD_C
25
OUT_C
24
GND_C
23
GND_D
22
OUT_D
21
PVDD_D
20
BST_D
19
GVDD_D
NAME
AGND
BST_A
BST_B
BST_C
BST_D
GND
GND_A
GND_B
GND_C
GND_D
GVDD_A
GVDD_B
GVDD_C
GVDD_D
M1
M2
M3
NC
OC_ADJ
OTW
OUT_A
OUT_B
OUT_C
PIN
DRV8412
12
24
33
34
43
13
29
30
37
38
23
22
1
44
8
9
10
3, 4, 19, 20, 25, 42
14
21
DRV8432
9
35
28
27
20
8
32
31
24
23
36
1
18
19
13
12
11
—
7
2
28
33
31
30
36
25
Pin Functions
I/O TYPE ⁽¹⁾
DESCRIPTION
P
Analog ground
P
High side bootstrap supply (BST), external capacitor to OUT_A required
P
High side bootstrap supply (BST), external capacitor to OUT_B required
P
High side bootstrap supply (BST), external capacitor to OUT_C required
P
High side bootstrap supply (BST), external capacitor to OUT_D required
P
Ground
P
Power ground for half-bridge A
P
Power ground for half-bridge B
P
Power ground for half-bridge C
P
Power ground for half-bridge D
P
Gate-drive voltage supply
P
Gate-drive voltage supply
P
Gate-drive voltage supply
P
Gate-drive voltage supply
I
Mode selection pin
I
Mode selection pin
I
Reserved mode selection pin, AGND connection is recommended
—
No connection pin. Ground connection is recommended
O
Analog overcurrent programming pin, requires resistor to AGND
O
Overtemperature warning signal, open-drain, active-low. An internal pullup resistor
to VREG (3.3 V) is provided on output. Level compliance for 5-V logic can be
obtained by adding external pullup resistor to 5 V
O
Output, half-bridge A
O
Output, half-bridge B
O
Output, half-bridge C
(1) I = input, O = output, P = power, T = thermal
4
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