DRV8412_15 Datasheet, PDF (14/42 Pages) Texas Instruments – DRV84x2 Dual Full-Bridge PWM Motor Driver

DRV8412, DRV8432
SLES242G – DECEMBER 2009 – REVISED DECEMBER 2014
www.ti.com
Feature Description (continued)
• Ipeak = 15 A (below abs max rating)
(1)
Because an inductor usually saturates after reaching its current rating, it is recommended to use an inductor with
a doubled value or an inductor with a current rating well above the operating condition.
Table 2. Programming-Resistor Values and OC
Threshold
OC-ADJUST RESISTOR
VALUES (kΩ)
22 ⁽¹⁾
24
27
30
36
39
43
47
56
68
82
100
120
150
200
MAXIMUM CURRENT BEFORE OC
OCCURS (A)
11.6
10.7
9.7
8.8
7.4
6.9
6.3
5.8
4.9
4.1
3.4
2.8
2.4
1.9
1.4
(1) Recommended to use in OC Latching Mode Only
7.3.2.3 Overtemperature Protection
The DRV841x2 has a two-level temperature-protection system that asserts an active-low warning signal (OTW)
when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds
150°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-
impedance (Hi-Z) state and FAULT being asserted low. OTSD is latched in this case and RESET_AB and
RESET_CD must be asserted low to clear the latch.
7.3.2.4 Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the DRV841x2 fully protect the device in any power-up/down and brownout
situation. While powering up, the POR circuit resets the overcurrent circuit and ensures that all circuits are fully
operational when the GVDD_X and VDD supply voltages reach 9.8 V (typical). Although GVDD_X and VDD are
independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in
all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being asserted low.
The device automatically resumes operation when all supply voltage on the bootstrap capacitors have increased
above the UVP threshold.
7.3.3 Device Reset
Two reset pins are provided for independent control of half-bridges A/B and C/D. When RESET_AB is asserted
low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance (Hi-Z) state. Likewise,
asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high- impedance state.
To accommodate bootstrap charging prior to switching start, asserting the reset inputs low enables weak
pulldown of the half-bridge outputs.
A rising-edge transition on reset input allows the device to resume operation after a shut-down fault. For
example, when either or both half-bridge A and B have OC shutdown, a low to high transition of RESET_AB pin
will clear the fault and FAULT pin; when either or both half-bridge C and D have OC shutdown, a low to high
transition of RESET_CD pin will clear the fault and FAULT pin as well. When an OTSD occurs, both RESET_AB
and RESET_CD need to have a low to high transition to clear the fault and FAULT signal.
14
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