DRV8412_15 Datasheet, PDF (25/42 Pages) Texas Instruments – DRV84x2 Dual Full-Bridge PWM Motor Driver

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DRV8412, DRV8432
SLES242G – DECEMBER 2009 – REVISED DECEMBER 2014
Power Supplies (continued)
For a properly functioning bootstrap circuit, a small ceramic capacitor (an X5R or better) must be connected from
each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the
bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin
(GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is
shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an
application with PWM switching frequencies in the range from 10 kHz to 500 kHz, the use of 100-nF ceramic
capacitors (X5R or better), size 0603 or 0805, is recommended for the bootstrap supply. These 100-nF
capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power
stage FET fully turned on during the remaining part of the PWM cycle. In an application running at a switching
frequency lower than 10 kHz, the bootstrap capacitor might need to be increased in value.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pin (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a ceramic capacitor (X5R or better) placed as close as possible to each supply pin. It is
recommended to follow the PCB layout of the DRV841x2 EVM board.
The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 50-V power-
stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical
as facilitated by the internal power-on-reset circuit. Moreover, the DRV841x2 is fully protected against erroneous
power-stage turn-on due to parasitic gate charging. Thus, voltage-supply ramp rates (dv/dt) are non-critical within
the specified voltage range (see Recommended Operating Conditions of this data sheet).
9.3 System Power-Up and Power-Down Sequence
9.3.1 Powering Up
The DRV841x2 does not require a power-up sequence. The outputs of the H-bridges remain in a high impedance
state until the gate-drive supply voltage GVDD_X and VDD voltage are above the undervoltage protection (UVP)
voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required,
holding RESET_AB and RESET_CD in a low state while powering up the device is recommended. This allows
an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge
output.
9.3.2 Powering Down
The DRV841x2 does not require a power-down sequence. The device remains fully operational as long as the
gate-drive supply (GVDD_X) voltage and VDD voltage are above the UVP voltage threshold (see the Electrical
Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold
RESET_AB and RESET_CD low during power down to prevent any unknown state during this transition.
9.4 System Design Recommendations
9.4.1 VREG Pin
The VREG pin is used for internal logic and not recommended to be used as a voltage source for external
circuitry.
9.4.2 VDD Pin
The transient current in VDD pin could be significantly higher than average current through that pin. A low
resistive path to GVDD should be used. A 22-µF to 47-µF capacitor should be placed on VDD pin beside the
100-nF to 1-µF decoupling capacitor to provide a constant voltage during transient.
9.4.3 OTW Pin
OTW reporting indicates the device approaching high junction temperature. This signal can be used with MCU to
decrease system power when OTW is low in order to prevent OT shut down at a higher temperature.
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