DRV8412_15 Datasheet, PDF (12/42 Pages) Texas Instruments – DRV84x2 Dual Full-Bridge PWM Motor Driver

DRV8412, DRV8432
SLES242G – DECEMBER 2009 – REVISED DECEMBER 2014
www.ti.com
7.3 Feature Description
7.3.1 Error Reporting
The FAULT and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode
signaling to a PWM controller or other system-control device.
Any fault resulting in device shutdown, such as overtemperatue shutdown, overcurrent shutdown, or
undervoltage protection, is signaled by the FAULT pin going low. Likewise, OTW goes low when the device
junction temperature exceeds 125°C (see Table 1).
FAULT
0
0
1
1
OTW
0
1
0
1
Table 1. Protection Mode Signal Descriptions
DESCRIPTION
Overtemperature warning and (overtemperature shut-down or overcurrent shut-down or undervoltage
protection) occurred
Overcurrent shut-down or GVDD undervoltage protection occurred
Overtemperature warning
Device under normal operation
TI recommends monitoring the OTW signal using the system microcontroller and responding to an OTW signal
by reducing the load current to prevent further heating of the device resulting in device overtemperature
shutdown (OTSD).
To reduce external component count, an internal pullup resistor to VREG (3.3 V) is provided on both FAULT and
OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the
Electrical Characteristics section of this data sheet for further specifications).
7.3.2 Device Protection System
The DRV841x2 contains advanced protection circuitry carefully designed to facilitate system integration and ease
of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as
short circuits, overcurrent, overtemperature, and undervoltage. The DRV841x2 responds to a fault by
immediately setting the half bridge outputs in a high-impedance (Hi-Z) state and asserting the FAULT pin low. In
situations other than overcurrent or overtemperature, the device automatically recovers when the fault condition
has been removed or the gate supply voltage has increased. For highest possible reliability, reset the device
externally no sooner than 1 second after the shutdown when recovering from an overcurrent shut down (OCSD)
or OTSD fault.
7.3.2.1 Bootstrap Capacitor Undervoltage Protection
When the device runs at a low switching frequency (for example, less than 10 kHz with a 100-nF bootstrap
capacitor), the bootstrap capacitor voltage might not be able to maintain a proper voltage level for the high-side
gate driver. A bootstrap capacitor undervoltage protection circuit (BST_UVP) will prevent potential failure of the
high-side MOSFET. When the voltage on the bootstrap capacitors is less than the required value for safe
operation, the DRV841x2 will initiate bootstrap capacitor recharge sequences (turn off high side FET for a short
period) until the bootstrap capacitors are properly charged for safe operation. This function may also be activated
when PWM duty cycle is too high (for example, less than 20 ns off time at 10 kHz). Note that bootstrap capacitor
might not be able to be charged if no load or extremely light load is presented at output during BST_UVP
operation, so it is recommended to turn on the low side FET for at least 50 ns for each PWM cycle to avoid
BST_UVP operation if possible.
For applications with lower than 10-kHz switching frequency and not to trigger BST_UVP protection, a larger
bootstrap capacitor can be used (for example, 1-µF capacitor for 800-Hz operation). When using a bootstrap cap
larger than 220 nF, it is recommended to add 5-Ω resistors between 12-V GVDD power supply and GVDD_X
pins to limit the inrush current on the internal bootstrap circuitry.
7.3.2.2 Overcurrent (OC) Protection
The DRV841x2 has independent, fast-reacting current detectors with programmable trip threshold (OC threshold)
on all high-side and low-side power-stage FETs. There are two settings for OC protection through mode
selection pins: cycle-by-cycle (CBC) current limiting mode and OC latching (OCL) shut down mode.
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