DAC8564 Datasheet, PDF (5/46 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

DAC8564
www.ti.com
PIN CONFIGURATIONS
PW PACKAGE
TSSOP-16
(Top View)
SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
V_OUTA 1
V_OUTB 2
V_REFH/V_REFOUT 3
AV_DD 4
V_REFL 5
GND 6
V_OUTC ₇
V_OUTD ₈
DAC8564
16 LDAC
15 ENABLE
14 A1
13 A0
12 ^IOVDD
11 ^DIN
10 SCLK
9 SYNC
PIN DESCRIPTIONS
PIN NAME
DESCRIPTION
1
V_OUTA Analog output voltage from DAC A
2
V_OUTB Analog output voltage from DAC B
3
V_REFH/
V_REFOUT
Positive reference input / reference output 2.5V if internal reference used
4
AV_DD Power supply input, 2.7V to 5.5V
5
V_REFL Negative reference input
6
GND Ground reference point for all circuitry on the part
7
V_OUTC Analog output voltage DAC C
8
V_OUTD Analog output voltage DAC D
Level-triggered control input (active low). This is the frame synchronization signal for the input data. When SYNC goes
9
SYNC
low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output
updates following the 24th clock. If SYNC is taken high before the 24th clock edge, the rising edge of SYNC acts as
an interrupt, and the write sequence is ignored by the DAC8564. Schmitt-Trigger logic Input.
10
SCLK Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic Input.
11
D_IN
Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock input.
Schmitt-Trigger logic Input.
12
IOV_DD Digital input-output power supply
13
A0
Address 0—sets device address; see Table 5.
14
A1
Address 1—sets device address; see Table 5.
15 ENABLE Active low, ENABLE low connects the SPI interface to the serial port
16
LDAC Load DACs; rising edge triggered, loads all DAC registers
Copyright © 2007, Texas Instruments Incorporated
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