DAC8564 Datasheet, PDF (31/46 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

DAC8564
www.ti.com
SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
OPERATION EXAMPLES: DAC8564
For the following examples, ensure that DAC pins A0 and A1 are both connected to ground. Pins A0 and A1
must always match data bits DB22 and DB23 within the SPI write sequence/protocol. X = Don't care. Value can
be either '0' or '1'.
Example 1: Write to Data Buffer A Through Buffer D; Load DAC A Through DAC D Simultaneously
• 1st: Write to data buffer A:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
0
0
0
DB15 DB14 DB13 DB12 DB11–DB0
• 2nd: Write to data buffer B:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
0
1
0
DB15 DB14 DB13 DB12 DB11–DB0
• 3rd: Write to data buffer C:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
1
0
0
DB15 DB14 DB13 DB12 DB11–DB0
• 4th: Write to data buffer D and simultaneously update all DACs:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
1
0
0
1
1
0
DB15 DB14 DB13 DB12 DB11–DB0
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously settle to the specified values upon
completion of the 4th write sequence. (The DAC voltages update simultaneously after the 24th SCLK falling edge
of the fourth write cycle).
Example 2: Load New Data to DAC A Through DAC D Sequentially
• 1st: Write to data buffer A and load DAC A: DAC A output settles to specified value upon completion:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
0
0
0
DB15 DB14 DB13 DB12 D11–DB0
• 2nd: Write to data buffer B and load DAC B: DAC B output settles to specified value upon completion:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
0
1
0
DB15 DB14 DB13 DB12 D11–DB0
• 3rd: Write to data buffer C and load DAC C: DAC C output settles to specified value upon completion:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
1
0
0
DB15 DB14 DB13 DB12 D11–DB0
• 4th: Write to data buffer D and load DAC D: DAC D output settles to specified value upon completion:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
1
1
0
DB15 DB14 DB13 DB12 D11–DB0
After completion of each write cycle, DAC analog output settles to the voltage specified.
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): DAC8564
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