DAC8564 Datasheet, PDF (28/46 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

DAC8564
SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
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LD1 (DB21) and LD0 (DB20) control the loading of
each analog output with the specified 16-bit data
value or power-down command. Bit DB19 must
always be '0'. The DAC channel select bits (DB18,
DB17) control the destination of the data (or
power-down command) from DAC A through DAC D.
The final control bit, PD0 (DB16), selects the
power-down mode of the DAC8564 channels as well
as the power-down mode of the internal reference.
The DAC8564 supports a number of different load
commands. The load commands include broadcast
commands to address all the DAC8564s on an SPI
bus. The load commands are summarized as follows:
DB21 = 0 and DB20 = 0: Single-channel store. The
data buffer corresponding to a DAC selected by
DB18 and DB17 updates with the contents of SR
data (or power-down).
DB21 = 0 and DB20 = 1: Single-channel update.
The data buffer and DAC register corresponding to a
DAC selected by DB18 and DB17 update with the
contents of SR data (or power-down).
DB21 = 1 and DB20 = 0: Simultaneous update. A
channel selected by DB18 and DB17 updates with
the SR data; simultaneously, all the other channels
update with previously stored data (or power-down)
from data buffers.
DB21 = 1 and DB20 = 1: Broadcast update. All the
DAC8564s on the SPI bus respond, regardless of
address matching. If DB18 = 0, SR data are ignored
and any channels from all DAC8564s update with
previously stored data (or power-down). If DB18 = 1,
SR data (or power-down) update any channels of all
DAC8564s in the system. This broadcast update
feature allows the simultaneous update of up to 16
channels.
Refer to Table 5 for more information.
DB23 DB22
A1
A0
(Address Select)
0/1
0/1
DB21
LD 1
DB20
LD 0
DB19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A0 and A1 should
correspond to the
package address
0
1
0
set via pins 13
and 14
0
1
0
1
0
0
1
0
0
X
X
1
1
0
X
X
1
1
0
X
X
1
1
0
Table 5. Control Matrix for the DAC8564
DB18
DAC Sel 1
DB17
DAC Sel 0
DB16
PD0
See Below
0
0
0
0
1
0
1
0
0
1
1
0
(00, 01, 10, or 11)
1
(00, 01, 10, or 11)
0
(00, 01, 10, or 11)
1
(00, 01, 10, or 11)
0
(00, 01, 10, or 11)
1
Broadcast Modes
0
X
X
1
X
0
1
X
1
DB15
MSB
DB14
MSB-1
DB13-DB0
MSB-2...LSB
Data
Data
Data
Data
See Table 6
0
Data
See Table 6
0
Data
See Table 6
0
X
Data
See Table 6
0
DESCRIPTION
This address selects 1 of 4 possible devices on a
single SPI data bus based on each device's address
pin(s) state.
Write to buffer A with data
Write to buffer B with data
Write to buffer C with data
Write to buffer D with data
Write to buffer (selected by DB17 and DB18) with
power-down command
Write to buffer with data and load DAC (selected by
DB17 and DB18)
Write to buffer with power-down command and load
DAC (selected by DB17 and DB18)
Write to buffer with data (selected by DB17 and DB18)
and then load all DACs simultaneously from their
corresponding buffers
Write to buffer with power-down command (selected by
DB17 and DB18) and then load all DACs
simultaneously from their corresponding buffers
Simultaneously update all channels of all DAC8554
devices in the system with data stored in each
channels data buffer
Write to all devices and load all DACs with SR data
Write to all devices and load all DACs with power-down
command in SR
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