DAC8564 Datasheet, PDF (25/46 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

DAC8564
www.ti.com
SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER (DAC)
The DAC8564 architecture consists of a string DAC
followed by an output buffer amplifier. Figure 92
shows a block diagram of the DAC architecture.
DAC
Register
V_REFH
50kW
62kW
REF(+)
Resistor String
REF(-)
50kW
V_OUTX
V_REFL
Figure 92. DAC8564 Architecture
The input coding to the DAC8564 is straight binary,
so the ideal output voltage is given by Equation 1.
V_OUTX + 2
V_REFL ) (V_REFH * V_REFL)
D_IN
65536 (1)
where D_IN = decimal equivalent of the binary code
that is loaded to the DAC register; it can range from 0
to 65535. X represents channel A, B, C, or D.
RESISTOR STRING
The resistor string section is shown in Figure 93. It is
simply a string of resistors, each of value R. The
code loaded into the DAC register determines at
which node on the string the voltage is tapped off to
be fed into the output amplifier by closing one of the
switches connecting the string to the amplifier. It is
monotonic because it is a string of resistors.
V_REF
R_DIVIDER
V_REF
2
R
R
To Output Amplifier
(2x Gain)
R
R
Figure 93. Resistor String
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating
rail-to-rail voltages on its output, giving an output
range of 0V to AV_DD. It is capable of driving a load of
2kΩ in parallel with 1000pF to GND. The source and
sink capabilities of the output amplifier can be seen in
the Typical Characteristics. The slew rate is 2.2V/µs,
with a full-scale settling time of 8µs with the output
unloaded.
Copyright © 2007, Texas Instruments Incorporated
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