DAC8564 Datasheet, PDF (32/46 Pages) Texas Instruments – 16-Bit, Quad Channel, Ultra-Low Glitch, Voltage Output DIGITAL-TO-ANALOG CONVERTER with 2.5V, 2ppm/°C Internal Reference

DAC8564
SBAS403A – JUNE 2007 – REVISED NOVEMBER 2007
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Example 3: Power-Down DAC A and DAC B to 1kΩ and Power-Down DAC C and DAC D to 100kΩ
Simultaneously
• 1st: Write power-down command to data buffer A: DAC A to 1kΩ.
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
0
0
1
0
1
X
X
X
• 2nd: Write power-down command to data buffer B: DAC B to 1kΩ.
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
0
1
1
0
1
X
X
X
• 3rd: Write power-down command to data buffer C: DAC C to 100kΩ.
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
0
0
1
0
1
1
0
X
X
X
• 4th: Write power-down command to data buffer D: DAC D to 100kΩ and simultaneously update all DACs.
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13 DB12 DB11–DB0
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
1
0
0
1
1
1
1
0
X
X
X
The DAC A, DAC B, DAC C, and DAC D analog outputs simultaneously power-down to each respective specified
mode upon completion of the fourth write sequence.
Example 4: Power-Down DAC A Through DAC D to High-Impedance Sequentially
• 1st: Write power-down command to data buffer A and load DAC A: DAC A output = Hi-Z:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
0
0
1
1
1
X
• 2nd: Write power-down command to data buffer B and load DAC B: DAC B output = Hi-Z:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
0
1
1
1
1
X
• 3rd: Write power-down command to data buffer C and load DAC C: DAC C output = Hi-Z:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
1
0
1
1
1
X
• 4th: Write power-down command to data buffer D and load DAC D: DAC D output = Hi-Z:
A1
A0 DB21 DB20 DB19
DB18
DB17
DB16 DB15 DB14 DB13
(LD1) (LD0)
(DAC Sel 1) (DAC Sel 0) (PD0)
0
0
0
1
0
1
1
1
1
1
X
DB12
X
DB12
X
DB12
X
DB12
X
DB11–DB0
X
DB11–DB0
X
DB11–DB0
X
DB11–DB0
X
The DAC A, DAC B, DAC C, and DAC D analog outputs sequentially power-down to high-impedance upon
completion of the first, second, third, and fourth write sequences, respectively.
32
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