BQ24190_15 Datasheet, PDF (5/52 Pages) Texas Instruments – bq2419x I2C Controlled 4.5-A Single Cell USB/Adapter Charger with Narrow VDC Power Path Management and USB OTG

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bq24190, bq24192, bq24192I
SLUSAW5B – JANUARY 2012 – REVISED DECEMBER 2014
Pin Functions (continued)
PIN
bq24190
bq24192
bq24192I
ILIM
ILIM
TS1
TS1
TS2
BAT
SYS
TS2
BAT
SYS
PGND
PGND
SW
BTST
SW
BTST
REGN
REGN
PMID
Thermal
Pad
PMID
–
NUMBER
10
11
12
13,14
15,16
17,18
19,20
21
22
23
–
TYPE
DESCRIPTION
I
Analog
ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1 V. A resistor is connected from
ILIM pin to ground to set the maximum limit as I_INMAX = (1V/R_ILIM) × 530. The actual input current limit is the
lower one set by ILIM and by I²C REG00[2:0]. The minimum input current programmed on ILIM pin is 500 mA.
I
Analog
Temperature qualification voltage input #1. Connect a negative temperature coefficient thermistor. Program
temperature window with a resistor divider from REGN to TS1 to GND. Charge suspends when either TS pin is
out of range. Recommend 103AT-2 thermistor.
I
Temperature qualification voltage input #2. Connect a negative temperature coefficient thermistor. Program
Analog
temperature window with a resistor divider from REGN to TS2 to GND. Charge suspends when either TS pin is
out of range. Recommend 103AT-2 thermistor.
P
Battery connection point to the positive terminal of the battery pack. The internal BATFET is connected
between BAT and SYS. Connect a 10 µF closely to the BAT pin.
System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls
P below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage.
(Refer to Application Information Section for inductor and capacitor selection.)
Power ground connection for high-current power converter node. Internally, PGND is connected to the source
P
of the n-channel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors
of the charger. A single point connection is recommended between power PGND and the analog GND near the
IC PGND pin.
O Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel
Analog HSFET and the drain of the n-channel LSFET. Connect the 0.047-µF bootstrap capacitor from SW to BTST.
P
PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode.
Connect the 0.047-µF bootstrap capacitor from SW to BTST.
PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-strap
P diode. Connect a 4.7-µF (10-V rating) ceramic capacitor from REGN to analog GND. The capacitor should be
placed close to the IC. REGN also serves as bias rail of TS1 and TS2 pins.
O
Analog
Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. Given the total input
capacitance, connect a 1-µF capacitor on VBUS to PGND, and the rest all on PMID to PGND. (Refer to
Application Information Section for details)
P
Exposed pad beneath the IC for heat dissipation. Always solder thermal pad to the board, and have vias on the
thermal pad plane star-connecting to PGND and ground plane for high-current power converter.
8 Specifications
8.1 Absolute Maximum Ratings⁽¹⁾
over operating free-air temperature range (unless otherwise noted)
Voltage range (with
respect to GND)
Output sink current
Junction temperature
Storage temperature, T_stg
VBUS
PMID
STAT, PG
BTST
SW
BAT, SYS (converter not switching)
SDA, SCL, INT, OTG, ILIM, REGN, TS1, TS2, CE, PSEL, D+, D–
BTST TO SW
PGND to GND
INT, STAT, PG
MIN
–2
–0.3
–0.3
–0.3
–2
–0.3
–0.3
–0.3
–0.3
–40°C
–65
MAX
22
22
20
26
20
6
7
–7
–0.3
6
150
150
UNIT
V
V
V
V
V
V
V
V
V
mA
°C
°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
Copyright © 2012–2014, Texas Instruments Incorporated
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