BQ24190_15 Datasheet, PDF (26/52 Pages) Texas Instruments – bq2419x I2C Controlled 4.5-A Single Cell USB/Adapter Charger with Narrow VDC Power Path Management and USB OTG

bq24190, bq24192, bq24192I
SLUSAW5B – JANUARY 2012 – REVISED DECEMBER 2014
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9.3.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)
The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter
that the byte was successfully received and another byte may be sent. All clock pulses, including the
acknowledge 9^th clock pulse, are generated by the master.
The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line
LOW and it remains stable LOW during the HIGH period of this clock pulse.
When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then
generate either a STOP to abort the transfer or a repeated START to start a new transfer.
9.3.6.5 Slave Address and Data Direction Bit
After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction
bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).
SDA
SCL
S
START
1-7
ADDRESS
8
9
1-7
8
9
R/W ACK
DATA
ACK
Figure 20. Complete Data Transfer
1-7
8
DATA
9
ACK
P
STOP
9.3.6.5.1 Single Read and Write
1
7
1
1
S Slave Address 0 ACK
8
Reg Addr
1
ACK
8
Data Addr
1
1
ACK P
Figure 21. Single Write
1
7
1
1
S Slave Address 0 ACK
8
Reg Addr
1
1
7
1
1
ACK S Slave Address 1 ACK
8
Data
1
1
NCK P
Figure 22. Single Read
If the register address is not defined, the charger IC send back NACK and go back to the idle state.
9.3.6.5.2 Multi-Read and Multi-Write
The charger device supports multi-read and multi-write on REG00 through REG08.
1
7
1
1
S Slave Address 0 ACK
8
Reg Addr
1
ACK
8
Slave Address
1
ACK
8
Data to Addr+1
1
ACK
8
Data to Addr+1
1
1
ACK P
Figure 23. Multi-Write
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