BQ24190_15 Datasheet, PDF (24/52 Pages) Texas Instruments – bq2419x I2C Controlled 4.5-A Single Cell USB/Adapter Charger with Narrow VDC Power Path Management and USB OTG

bq24190, bq24192, bq24192I
SLUSAW5B – JANUARY 2012 – REVISED DECEMBER 2014
www.ti.com
9.3.5.4 Voltage and Current Monitoring in Boost Mode
The bq24190, bq24192, bq24192I closely monitors the VBUS voltage, as well as HSFET and LSFET current to
ensure safe boost mode operation.
9.3.5.4.1 VBUS Over-Voltage Protection
The boost mode regulated output is 5 V. When an adapter plugs in during boost mode, the VBUS voltage will
rise above regulation target. Once the VBUS voltage exceeds 5.3 V, the bq24190, bq24192, bq24192I stops
switching and the device exits boost mode. The fault register REG09[6] is set high to indicate fault in boost
operation. An INT is asserted to the host.
9.3.5.5 Battery Protection
9.3.5.5.1 Battery Over-Current Protection (BATOVP)
The battery over-voltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage
occurs, the charger device immediately disables charge. The fault register REG09[5] goes high and an INT is
asserted to the host.
9.3.5.5.2 Charging During Battery Short Protection
If the battery voltage falls below 2 V, the charge current is reduced to 100 mA for battery safety.
9.3.5.5.3 System Over-Current Protection
If the system is shorted or exceeds the over-current limit, the BATFET is latched off. DC source insertion on
VBUS is required to reset the latch-off condition and turn on BATFET.
9.3.6 Serial Interface
The bq24190, bq24192, bq24192I uses I²C compatible interface for flexible charging parameter programming
and instantaneous device status reporting. I²C is a bi-directional 2-wire serial interface developed by Philips
Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial
clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is
the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At
that time, any device addressed is considered a slave.
The device operates as a slave device with address 6BH, receiving control inputs from the master device like
micro controller or a digital signal processor. The I²C interface supports both standard mode (up to 100 kbits),
and fast mode (up to 400 kbits).
Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pull-
up resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain.
9.3.6.1 Data Validity
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the
data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each
data bit transferred.
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