BQ24190_15 Datasheet, PDF (25/52 Pages) Texas Instruments – bq2419x I2C Controlled 4.5-A Single Cell USB/Adapter Charger with Narrow VDC Power Path Management and USB OTG

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SLUSAW5B – JANUARY 2012 – REVISED DECEMBER 2014
SDA
SCL
Data line stable;
Data valid
Change
of data
allowed
Figure 17. Bit Transfer on the I²C Bus
9.3.6.2 START and STOP Conditions
All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the
SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the
SCL is HIGH defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered busy after the START
condition, and free after the STOP condition.
SDA
SDA
SCL
SCL
START (S)
Figure 18. START and STOP conditions
STOP (P)
9.3.6.3 Byte Format
Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is
unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant
Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some
other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data
transfer then continues when the slave is ready for another byte of data and release the clock line SCL.
SDA
MSB
Acknowledgement
signal from slave
Acknowledgement
signal from receiver
SCL
S or Sr
START or
Repeated
START
1
2
7
8
9
ACK
1
2
Figure 19. Data Transfer on the I²C Bus
8
9
ACK
P or Sr
STOP or
Repeated
START
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