BQ24160A_15 Datasheet, PDF (5/52 Pages) Texas Instruments – bq2416xx 2.5A, Dual-Input, Single-Cell Switched-Mode Li-Ion Battery Charger with Power Path Management and I2C Interface

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bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0F – NOVEMBER 2011 – REVISED JULY 2014
NAME
BAT
BGATE
BOOT
CD
D+
D–
DRV
IN
INT
PGND
PMIDI
PMIDU
PSEL
SCL
SDA
STAT
SW
SYS
TS
USB
Thermal
Pad
PIN
NO.
bq24160, 3
YFF
RGE
G1-G4 11, 12
F5
10
E7
19
E4
24
E2
2
E3
1
F7
6
A1- A4
21
F6
7
D1-D7,
E1, G7
B1-B4
5, 15,
16, 17
20
B5-B7
23
—
—
E6
3
E5
4
G6
8
C1-C7
F1-F4
18
13, 14
G5
9
A5-A7
22
—
Pad
Pin Functions
NO.
bq24161, 1B, 8
YFF
RGE
G1-G4 11, 12
F5
10
E7
19
E4
24
—
—
—
—
F7
6
A1- A4
21
F6
7
D1-D7,
E1, G7
B1-B4
5, 15,
16, 17
20
B5-B7
23
E2
2
E6
3
E5
4
G6
8
C1-C7
F1-F4
18
13,14
G5
9
A5-A7
22
—
Pad
I/O
DESCRIPTION
I/O Battery Connection – Connect to the positive terminal of the battery. Additionally, bypass BAT
to GND with at least a 1μF capacitor.
O External Discharge MOSFET Gate Connection – BGATE drives an external P-Channel
MOSFET to provide a very low-resistance discharge path. Connect BGATE to the gate of the
external MOSFET. BGATE is low during high impedance mode and when no input is connected.
I High Side MOSFET Gate Driver Supply – Connect a 0.01µF ceramic capacitor (voltage rating
> 10V) from BOOT to SW to supply the gate drive for the high side MOSFETs.
I IC Hardware Chip Disable Input – Drive CD high to place the bq2416xx in high-z mode. Drive
CD low for normal operation. Do not leave CD unconnected.
I D+ and D– Connections for USB Input Adapter Detection – When a charge cycle is initiated
I
by the USB input, and a short is detected between D+ and D–, the USB input current limit is set
to 1.5A. If a short is not detected, the USB100 mode is selected. The D+/D– detection has no
effect on the IN input.
O Gate Drive Supply – DRV is the bias supply for the gate drive of the internal MOSFETs. Bypass
DRV to PGND with a 1μF ceramic capacitor. DRV may be used to drive external loads up to
10mA. DRV is active whenever the input is connected and V_SUPPLY > V_UVLO and V_SUPPLY > (V_BAT
+ V_SLP)
I Input power supply – IN is connected to the external DC supply (AC adapter or alternate power
source). Bypass IN to PGND with at least a 1μF ceramic capacitor.
O Status Output – INT is an open-drain output that signals charging status and fault interrupts.
INT pulls low during charging. INT is high impedance when charging is complete or the charger
is disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host. INT is
enabled/disabled using the EN_STAT bit in the control register. Connect INT to a logic rail
through a 100kΩ resistor to communicate with the host processor.
— Ground terminal – Connect to the thermal pad (for VQFN only) and the ground plane of the
circuit.
O Reverse Blocking MOSFET and High Side MOSFET Connection Point for High Power
Input – Bypass PMIDI to GND with at least a 4.7μF ceramic capacitor. Use caution when
connecting an external load to PMIDI. The PMIDI output is not current limited. Any short on
PMIDI will damage the IC.
O Reverse Blocking MOSFET and High Side MOSFET Connection Point for USB Input –
Bypass PMIDU to GND with at least a 4.7μF ceramic capacitor. Use caution when connecting
an external load to PMIDU. The PMIDU output is not current limited. Any short on PMIDU will
damage the IC.
USB Source Detection Input – Drive PSEL high to indicate that a USB source is connected to
the USB input. When PSEL is high, the IC starts up with a 100mA (bq24161/8) or 500mA
(bq24161B) input current limit for USB. Drive PSEL low to indicate that an AC Adapter is
connected to the USB input. When PSEL is low, the IC starts up with a 1.5A input current limit
for USB. PSEL has no effect on the IN input. Do not leave PSEL unconnected.
I I²C Interface Clock – Connect SCL to the logic rail through a 10kΩ resistor.
I/O I²C Interface Data – Connect SDA to the logic rail through a 10kΩ resistor.
O Status Output – STAT is an open-drain output that signals charging status and fault interrupts.
STAT pulls low during charging. STAT is high impedance when charging is complete or the
charger is disabled. When a fault occurs, a 128μs pulse is sent out as an interrupt for the host.
STAT is enabled /disabled using the EN_STAT bit in the control register. Pull STAT up to a logic
rail thruogh an LED for visual indication or through a 10kΩ resistor to communicate with the host
processor.
O Inductor Connection – Connect to the switched side of the external inductor.
I System Voltage Sense and Charger FET Connection – Connect SYS to the system output at
the output bulk capacitors. Bypass SYS locally with at least 10μF. A 47μF bypass capacitor is
recommended for optimal transient response.
I Battery Pack NTC Monitor – Connect TS to the center tap of a resistor divider from DRV to
GND. The NTC is connected from TS to GND. The TS function provides 4 thresholds for JEITA
compatibility (160, 161B, 163, 168 only). TS faults are reported by the I²C interface. See the
NTC Monitor section for more details on operation and selecting the resistor values. Connect TS
to DRV to disable the TS function.
I USB Input Power Supply – USB is connected to the external DC supply (AC adapter or USB
port). Bypass USB to PGND with at least a 1μF ceramic capacitor.
— There is an internal electrical connection between the exposed thermal pad and the PGND pin
of the device. The thermal pad must be connected to the same potential as the PGND pin on the
printed circuit board. Do not use the thermal pad as the primary ground input for the device.
PGND pin must be connected to ground at all times.
Copyright © 2011–2014, Texas Instruments Incorporated
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Product Folder Links: bq24160 bq24160A bq24161 bq24161B bq24163 bq24168