BQ24160A_15 Datasheet, PDF (27/52 Pages) Texas Instruments – bq2416xx 2.5A, Dual-Input, Single-Cell Switched-Mode Li-Ion Battery Charger with Power Path Management and I2C Interface

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Programming (continued)
DATA
bq24160, bq24160A, bq24161
bq24161B, bq24163, bq24168
SLUSAO0F – NOVEMBER 2011 – REVISED JULY 2014
CLK
Data Line
Stable
Data Valid
Chang
of Data
Allowed
Figure 18. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary. To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line
from low to high while the SCL line is high (see Figure 20). This releases the bus and stops the communication
link with the addressed slave. All I²C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching
address. If a transaction is terminated prematurely, the master needs sending a STOP condition to prevent the
slave I²C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in
this section result in FFh being read out.
Data Output
by Transmitter
Data Output
by Receiver
SCL From
Master
S
START
Condition
Not Acknowledge
1
2
Acknowledge
8
9
Clock Pulse for
Acknowledgement
Figure 19. Acknowledge on the I2C Bus
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