TLC320AD56C Datasheet, PDF (41/43 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

FN (S-PQCC-J**)
20 PIN SHOWN
3
4
E E1
8
9
Appendix B
Mechanical Data
PLASTIC J-LEADED CHIP CARRIER
D
D1
1
19
0.032 (0,81)
0.026 (0,66)
18
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
0.020 (0,51) MIN
D2/E2
14
0.050 (1,27)
13
0.008 (0,20) NOM
D2/E2
0.021 (0,53)
0.013 (0,33)
0.007 (0,18) M
NO. OF
PINS
**
D/E
MIN
MAX
D1 / E1
MIN
MAX
D2 / E2
MIN
MAX
20
0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29)
28
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58) 0.191 (4,85) 0.219 (5,56)
44
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66) 0.291 (7,39) 0.319 (8,10)
52
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20) 0.341 (8,66) 0.369 (9,37)
68
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
84
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
B–1