TLC320AD56C Datasheet, PDF (33/43 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

4.3.10 Power-Supply Rejection (see Note 10)
PARAMETER
TEST CONDITIONS MIN TYP† MAX UNIT
VDD1
Supply-voltage rejection ratio, ADC channel,
DVDD
fi = 0 to 30 kHz
55
dB
VDD2
Supply-voltage rejection ratio, DAC channel,
DVDD
fi = 0 to 30 kHz
55
dB
VDD3
Supply-voltage rejection ratio, ADC channel,
AVDD
fi = 0 to 30 kHz
50
dB
VDD4
Supply-voltage rejection ratio, DAC channel,
AVDD
† _{All typical values are at 25°C.}
Single ended,
fi = 0 to 30 kHz
Differential,
fi = 0 to 30 kHz
50
dB
55
dB
NOTE 10: Power supply rejection measurements are made with both the ADC and the DAC channels idle and a 200-mV
peak-to-peak signal applied to the appropriate supply.
4.3.11 Timing Requirements (see Figure 3–1)
PARAMETER
TEST CONDITIONS
td1 Delay time, SCLK↑ to FS↓
td2 Delay time, SCLK↑ to DOUT valid
tsu DIN setup time before SCLK low
th
DIN hold time after SCLK high
ten Enable time, FS↓ to DOUT valid
tdis Disable time, FS↑ to DOUT Hi-Z
td3 Delay time, MCLK↓ to SCLK↑
CL = 20 pF
twH Pulse duration, MCLK high
twL Pulse duration, MCLK low
MIN TYP MAX UNIT
0
20
20
20
25 ns
20
50
32
20
4–7