TLC320AD56C Datasheet, PDF (25/43 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

Communication Frame 1 (CF1)
(CF2)
FS _Primary
Secondary
Primary
No Secondary
Request
FC
0
ÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ _DIN
(Secondary
ÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ _{Read or Write)}
ÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏ _DOUT
D15-D1 D0 = 1
DAC Data
Software FC Bit
Secondary
Update
8 SCLKs
D15-D1 D0 = 0
DAC Data
See Note A
(Secondary
Read)
ADC Data
ADC Data
Register
Data
DOUT
(Secondary ^{ADC Data}
All Bits 0
ADC Data
Write)
16 SCLKs
16 SCLKs
16 SCLKs
32 FCLKs
64 FCLKs
64 FCLKs
NOTE A: For a read cycle, the last 8 bits are do-not-care bits.
Figure 3–4. Software FC Secondary Request (Phone Mode Disabled)
Table 3–3 shows the secondary communications format. D13 is the read/not-write (R/W) bit.
D12–D8 are address bits. The register map is specified in the register set section in Appendix A. D7–D0
are data bits. The data bits are the new values for the specified register addressed by D12–D8.
Table 3–3. Secondary Communication Data Format
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
–– –– R/W A
A
A
A
A
D
D
D
D
D
D
D
D
3–5