TLC320AD56C Datasheet, PDF (24/43 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

Communication Frame 1 (CF1)
(CF2)
FS _Primary
Secondary
Primary
No Secondary
Request
FC ÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏ
8 SCLKs
DOUT
(Secondary
Read)
ADC Data
Out
Register
ADC Data
Out
Data
DOUT
(Secondary
Write)
DIN
(Secondary
Read or Write)
ADC Data
All Bits 0
ADC Data
Out
Out
ÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏÏÏÏÏ _DACDataIn
Secondary
Update
DAC Data In
16 SCLKs
16 SCLKs
16 SCLKs
32 FCLKs
64 FCLKs
64 FCLKs
Figure 3–3. Hardware FC Secondary Request
(Phone Mode Disabled)
In Figure 3–4, FC hardware terminal 15 is left in its unasserted state (0). FC is asserted through software
by embedding an asserted high level (1) in the LSB of the 16-bit primary word. This is possible when not
in 16-bit mode (Control 1 register, bit 2 = 0) because the user is using only 15 bits of DAC information.
3–4