TLC320AD56C Datasheet, PDF (17/43 Pages) Texas Instruments – Sigma-Delta Analog Interface Circuit

2.2.1.2 Conditions of Reset
The two internal reset signals used for the reset and synchronization functions are:
1. Counter Reset – This signal resets all flip-flops and latches that are not externally programmed,
with the exception of those generating the reset pulse itself. Additionally, this
signal resets the software power-down bit. A counter reset is initiated with the
RESET terminal or RESET bit or PWRDWN terminal.
2. Register Reset – This signal resets all flip-flops and latches that are not reset by the counter
reset, except those generating the reset pulse itself. A register reset is initiated
with the RESET terminal or RESET bit.
Both reset signals should be at least six master clock periods long, T_RESET, and should release on the trailing
edge of the master clock.
2.2.1.3 Software and Hardware Power Down
Given the definitions above, the software programmed power-down condition is cleared by clearing the
software bit (Control 1 register, bit 6) to a 0 or by cycling the power to the device or bringing RESET low.
The output of the monitor amplifier maintains its midpoint voltage during hardware and software power
downs to minimize pops and clicks.
PWRDWN powers down the entire chip. Cycling the power-down terminal from high to low and back high
resets all flip-flops and latches that are not externally programmed, thereby preserving the register contents.
When PWRDWN is not used, it should be tied high.
2.2.2 Master Clock Circuit
The clock circuit generates and distributes necessary clocks throughout the device. MCLK is the external
master clock input. SCLK is derived from MCLK in order to provide clocking of the serial communications
between the device and a digital signal processor (DSP). The sample rates of the data paths are set to
MCLK/512.
2.2.3 Data Out (DOUT)
DOUT is taken from the high-impedance state by the falling edge of frame sync. The most significant data
bit then appears on DOUT.
DOUT is placed in a high-impedance state on the sixteenth rising edge of SCLK after the falling edge of
frame sync. In the primary communication, the data word is the ADC conversion result. In the secondary
communication, the data is the register read results when requested by the read/ write (R / W) bit with the
eight MSBs set to 0 (see Section 3 Serial Communications). If no register read is requested, the secondary
word is all zeroes.
2.2.4 Data In (DIN)
In the primary communication, the data word is the input digital signal to the DAC channel. In the secondary
communication, the data is the control and configuration data to set up the device for a particular function.
(see section 3 Serial Communications).
2.2.5 Hardware Program Terminal (FC)
FC provides for hardware programming requests for secondary communication. It works in conjunction with
the control bit D00 of the secondary data word. The signal on FC is latched 1/2 shift clock after the rising
edge of the next internally generated primary frame-sync interval. The FC terminal should be tied low when
not used (see Section 3.2 Secondary Serial Communication and Table 3–2).
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