TLC32046CFN Datasheet, PDF (40/56 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

SHIFT
CLK
FSX, FSR, FSD
DR
DX
DATA-DR
2V
2V
8V
td _(CH-FL)
8V
D15
D14
tsu _(DX)
D15 D14
D13
D13
td _(CH-DR)
D12 D11
D12 D11
tc _(SCLK)
2V
2V
8V
td _(CH-FH)
2V
D2
D1 D0
D2
D1
D0
Don’t Care
D15
D14
D13
D12 D11
D2
D1 D0
Figure 4–2. Dual-Word (Telephone Interface) Mode Timing
SHIFT
CLK
FSX, FSR^†
DR
2V
2V
8V
td _(CH-FL)
8V
D15
D14 D13
td _(CH–DR)
D12 D11
tc _(SCLK)
2V 2V
8V
td (CH-FH)
2V
D2
D1 D0
tsu _(DX)
DX
D15 D14 D13 D12 D11 D2
D1
D0
Don’t Care
EODX, EODR^‡
th _(DX)
td _(CH-EL)
8V
td _(CH-EH)
2V
Figure 4–3. Word Timing
† _{The time between falling edges of FSR is the A/D conversion period and the time between falling edges of FSX is the}
D/A conversion period.
‡ _{In the word format, EODX and EODR go low to signal the end of a 16-bit data word to the processor. The word-cycle}
is 20 shift-clocks wide, giving a four-clock period setup time between data words.
4–2