TLC32046CFN Datasheet, PDF (37/56 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

3.5.3 Serial Port – AIC Output Signals, C_L = 30 pF for SHIFT CLK Output, C_L = 15 pF
For All Other Outputs, TLC32046C and TLC32046I
PARAMETER
MIN TYP^† MAX UNIT
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
380
45%
ns
3
8 ns
3
8 ns
55%
td(CH-FL) Delay from SCLK↑ to FSR/FSX/FSD↓
td(CH-FH) Delay from SCLK↑ to FSR/FSX/FSD↑
td(CH-DR) DR valid after SCLK↑
td(CH-EL) Delay from SCLK↑ to EODX/EODR↓ in word mode
td(CH-EH) Delay from SCLK↑ to EODX/EODR↑ in word mode
tf(EODX) EODX fall time
tf(EODR) EODR fall time
td(CH-EL) Delay from SCLK↑ to EODX/EODR↓ in byte mode
td(CH-EH) Delay from SCLK↑ to EODX/EODR↑ in byte mode
td(MH-SL) Delay from MSTR CLK↑ to SCLK↓
td(MH-SH) Delay from MSTR CLK↑ to SCLK↑
† _{Typical values are at TA = 25°C.}
30
ns
35
90 ns
90 ns
90 ns
90 ns
2
8 ns
2
8 ns
90 ns
90 ns
65 170 ns
65 170 ns
3.5.4 Serial Port – AIC Output Signals, C_L = 30 pF for SHIFT CLK Output, C_L = 15 pF
For All Other Outputs, TLC32046M
PARAMETER
MIN TYP^† MAX UNIT
tc(SCLK)
tf(SCLK)
tr(SCLK)
Shift clock (SCLK) cycle time
Shift clock (SCLK) fall time
Shift clock (SCLK) rise time
Shift clock (SCLK) duty cycle
400
45%
ns
3
ns
3
ns
55%
td(CH-FL) Delay from SCLK↑ to FSR/FSX/FSD↓
td(CH-FH) Delay from SCLK↑ to FSR/FSX/FSD↑
td(CH-DR) DR valid after SCLK↑
td(CH-EL) Delay from SCLK↑ to EODX/EODR↓ in word mode
td(CH-EH) Delay from SCLK↑ to EODX/EODR↑ in word mode
tf(EODX) EODX fall time
tf(EODR) EODR fall time
td(CH-EL) Delay from SCLK↑ to EODX/EODR↓ in byte mode
td(CH-EH) Delay from SCLK↑ to EODX/EODR↑ in byte mode
td(MH-SL) Delay from MSTR CLK↑ to SCLK↓
td(MH-SH) Delay from MSTR CLK↑ to SCLK↑
† _{Typical values are at TA = 25°C.}
30 250 ns
35 250 ns
250 ns
250 ns
250 ns
2
ns
2
ns
250 ns
250 ns
65 170 ns
65 170 ns
3–7