TLC32046CFN Datasheet, PDF (17/56 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

XTAL
OSC
20.736 MHZ
41.472 MHZ
TMS320 DSP
5.184 MHz
MASTER CLOCK _{10.368 MHz}
Divide By 4
SHIFT CLOCK
1.296 MHz
2.592 MHz
Transmit Section
D/A Conversion
Timing
TA Register
(5 Bits)
See Table 2-3
TA′ REGISTER
(6 Bits)
2s-Complement TA
See Table 2-3
Adder/Subtractor
D1^† D0 SELECT
0 0 TA
0 1 TA + TA′
1 0 TA – TA′
1 1 TA
9
See Table 2-2
18
TB Register
(6 Bits)
See Table 2-3
TX (A) Counter
Divide By 2
TX (B) Counter
(6 Bits)
576 kHz
288 kHz
SCF CLOCK
Low-Pass Filter,
(sin x)/x Filter
7.20 kHz for TB = 40
8.00 kHz for TB = 36
9.60 kHz for TB = 30
14.4 kHz for TB = 20
16.0 kHz for TB = 18
19.2 kHz for TB = 15
D/A Conversion
Frequency
Receive Section
A/D Conversion
Timing
RA Register
(5 Bits)
See Table 2-3
RA′ Register
(6 Bits)
2s-Complement RA
See Table 2-3
Adder/Subtractor
D1^† D0 SELECT
0 0 RA
0 1 RA + RA′
1 0 RA – RA′
1 1 RA
9
18
See Table 2-2
RB Register
(6 Bits)
See Table 2-3
RX (A) Counter
(6 Bits)
Divide By 2
RX (B) Counter
576 kHz
288 kHz
SCF CLOCK
Low-Pass Filter
7.20 kHz for RB = 40
8.00 kHz for RB = 36
9.60 kHz for RB = 30
14.4 kHz for RB = 20
16.0 kHz for RB = 18
19.2 kHz for RB = 15
High-Pass Filter,
A/D Conversion
Frequency
† _{These control bits are described in the DX Serial Data Word Format section.}
NOTES: A. Tables 2–2 and 2–3 are primary and secondary communication protocols, respectively.
B. In synchronous operation, RA, RA’, RB, RX(A), and RX(B) are not used. TA, TA’, TB, TX(A), and TX(B) are
used instead.
C. Items in italics refer only to frequencies and register contents, which are variable. A crystal oscillator driving
20.736 MHz into the TMS320-series DSP provides a master clock frequency of 5.184 MHz. The TLC32046
produces a shift clock frequency of 1.296 MHz. If the TX(A) register contents equal 9, the SCF clock
frequency is 288 kHz, and the D/A conversion frequency is 288 kHz ÷ T(B).
Figure 2–1. Asynchronous Internal Timing Configuration
2–3