TLC32046CFN Datasheet, PDF (18/56 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

2.2 Analog Input
Two pairs of analog inputs are provided. Normally, the IN+ and IN– input pair is used; however, the auxiliary
input pair, AUX IN+ and AUX IN–, can be used if a second input is required. Since sufficient common-mode
range and rejection are provided, each input set can be operated in differential or single-ended modes. The
gain for the IN +, IN –, AUX IN +, and AUX IN – inputs can be programmed to 1, 2, or 4 (see Table 4 –1). Either
input circuit can be selected via software control. Multiplexing is controlled with the D4 bit (enable/disable
AUX IN+ and AUX IN –) of the secondary DX word (see Table 2–3). The multiplexing requires a 2-ms wait
at SCF = 288 kHz (see Figure 5–3) for a valid output signal. A wide dynamic range is ensured by the
differential internal analog architecture and the separate analog and digital voltage supplies and grounds.
2.3 A/D Band-Pass Filter, Clocking, and Conversion Timing
The receive-channel A/D high-pass filter can be selected or bypassed via software control (see Functional
Block Diagram). The frequency response of this filter is found in the electrical characteristic section. This
response results when the switched-capacitor filter clock frequency is 288 kHz and the A/D sample rate is
16 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter clock. When the
filter clock frequency is not 288 kHz, the low-pass filter transfer function is frequency-scaled by the ratio of
the actual clock frequency to 288 kHz (see Typical Characteristics section). The ripple bandwidth and 3-dB
low-frequency roll-off points of the high-pass section are 300 Hz and 200 Hz, respectively. However, the
high-pass section low-frequency roll-off is frequency-scaled by the ratio of the A/D sample rate to 16 kHz.
Figure 2–1 and the DX serial data word format sections of this data manual indicate the many options for
attaining a 288-kHz band-pass switched-capacitor filter clock. These sections indicate that the RX(A)
counter can be programmed to give a 288-kHz band-pass switched-capacitor filter clock for several master
clock input frequencies.
The A/D conversion rate is attained by frequency-dividing the band-pass switched-capacitor filter clock with
the RX(B) counter. Unwanted aliasing is prevented because the A/D conversion rate is an integer
submultiple of the band-pass switched-capacitor filter sampling rate, and the two rates are synchronously
locked.
2.4 A/D Converter
Fundamental performance specifications for the receive channel ADC circuitry are in the electrical
characteristic section of this data manual. The ADC circuitry, using switched-capacitor techniques, provides
an inherent sample-and-hold function.
2.5 Analog Output
The analog output circuitry is an analog output power amplifier. Both noninverting and inverting amplifier
outputs are brought out of the IC. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.
2.6 D/A Low-Pass Filter, Clocking, and Conversion Timing
The frequency response results when the low-pass switched-capacitor filter clock frequency is 288 kHz (see
equation 1). Like the A/D filter, the transfer function of this filter is frequency-scaled when the clock frequency
is not 288 kHz (see Typical Characteristics section). A continuous-time filter is provided on the output of the
low-pass filter to eliminate the periodic sample data signal information, which occurs at multiples of the
288-kHz switched-capacitor clock feedthrough.
The D/A conversion rate is attained by frequency-dividing the 288-kHz switched-capacitor filter clock with
the T(B) counter. Unwanted aliasing is prevented because the D/A conversion rate is an integer submultiple
of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously locked.
2.7 D/A Converter
Fundamental performance specifications for the transmit channel DAC circuitry are in the electrical
characteristic section. The DAC has a sample-and-hold function that is realized with a switched-capacitor
ladder.
2–4