TLC32046CFN Datasheet, PDF (20/56 Pages) Texas Instruments – Wide-Band Analog Interface Circuit

2.9.3 Synchronous Operating Frequencies
The synchronous operating frequencies are determined by the following equations.
Switched capacitor filter (SCF) frequencies (see Figure 2–1):
Low-pass SCF clock frequency
ń ń + (D A and A D channels)
master clock frequency
T(A) 2
ń + ń High-pass SCF clock frequency (A D channel) A D conversion frequency
ń ń + Conversion frequency (A D and D A channels)
low-pass SCF clock frequency
T(B)
+ master clock frequency
T(A) 2 T(B)
NOTE: T(A), T(B), R(A), and R(B) are the contents of the TA, TB, RA, and RB registers, respectively.
2.10 Asynchronous Operation
When the transmit and the receive sections are operated asynchronously, the low-pass and band-pass filter
clocks are independently generated from the master clock. The D/A and the A/D conversion timing is also
determined independently.
D/A timing is set by the counters and registers described in synchronous operation, but the RA and RB
registers are substituted for the TA and TB registers to determine the A/D channel sample rate and the A/D
path switched-capacitor filter frequencies. Asynchronous operation is selected by control register bit D5
being zero.
2.10.1 One 16-Bit Word (Word Mode)
The serial port interfaces directly with the serial ports of the TMS32020, TMS320C25, and TMS320C30 and
communicates with 16-bit word formats. The operation sequence is as follows:
1. FSX or FSR are brought low by the TLC32046 AIC.
2. One 16-bit word is transmitted or one 16-bit word is received.
3. FSX or FSR are brought high.
4. EODX or EODR emit low-going pulses one shift clock wide. EODX and EODR are valid in either
the word or byte mode only.
2.10.2 Two 8-Bit Bytes (Byte Mode)
The serial port interfaces directly with the serial port of the TMS320C17 and communicates in two 8-bit
bytes. The operating sequence is as follows:
1. FSX or FSR are brought low by the TLC32046 AIC.
2. One byte is transmitted or received.
3. EODX or EODR are brought low.
4. FSX or FSR are brought high for four shift clock periods and then brought low.
5. The second byte is transmitted or received.
6. FSX or FSR are brought high.
7. EODX or EODR are brought high.
2.10.3 Asynchronous Operating Frequencies
The asynchronous operating frequencies are determined by the following equations.
Switched-capacitor filter frequencies (see Figure 2–1):
ń + Low-pass D A SCF clock frequency
master clock frequency
T(A) 2
2–6