OMAPL137BPTPH Datasheet, PDF (40/205 Pages) Texas Instruments – Low-Power Applications Processor

OMAPL137-HT
SPRS677B – FEBRUARY 2012 – REVISED FEBRUARY 2013
www.ti.com
Table 2-19. Multichannel Audio Serial Ports (McASPs) Terminal Functions (continued)
SIGNAL NAME
ACLKX1/EPWM0A/GP3[15]
AFSX1/EPWMSYNCI/EPWMSYNCO/GP4[10]
ACLKR1/ECAP2/APWM2/GP4[12]
AFSR1/GP4[13]
AMUTE1/EPWMTZ/GP4[14]
AXR0[2]/RMII_TXEN/ AXR2[3]/GP3[2]
AXR0[3]/RMII_CRS_DV/ AXR2[2]/GP3[3]
AXR0[4]/RMII_RXD[0]/ AXR2[1]/GP3[4]
AXR0[11]/AXR2[0]/GP3[11]
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
AXR0[1]/RMII_TXD[1]/ ACLKX2/GP3[1]
AXR0[5]/RMII_RXD[1]/ AFSX2/GP3[5]
AXR0[6]/RMII_RXER[0]/ ACLKR2/GP3[6]
EMA_CS[3]/AMUTE2/GP2[6]
PIN NO
PTP
162
163
165
166
132
McASP2
113
115
116
124
125
112
117
118
21
TYPE⁽¹⁾ PULL⁽²⁾
MUXED
DESCRIPTION
I/O
IPD
eHRPWM0,
GPIO
McASP1
transmit bit
clock.
I/O
IPD
eHRPWM0,
GPIO
McASP1
transmit frame
sync.
I/O
IPD
eCAP2, GPIO
McASP1 receive
bit clock.
I/O
IPD GPIO
McASP1 receive
frame sync.
eHRPWM0,
O
IPD
eHRPWM1,
GPIO,
McASP1 mute
output.
eHRPWM2
I/O
IPD
I/O
IPD
McASP0,
EMAC, GPIO
McASP2 serial
I/O
IPD
data.
I/O
IPD
McASP0,
GPIO
McASP2
I/O
IPD
transmit master
McASP0, USB, ^clock.
GPIO
McASP2
I/O
IPD
transmit bit
clock.
I/O
IPD
McASP0,
EMAC, GPIO
McASP2
transmit frame
sync.
I/O
IPD
McASP0,
EMAC, GPIO
McASP2 receive
bit clock.
O
IPU
EMIFA, GPIO
McASP2 mute
output.
2.8.16 Universal Serial Bus Modules (USB0, USB1)
Table 2-20. Universal Serial Bus (USB) Terminal Functions
SIGNAL NAME
USB0_DM
USB0_DP
USB0_VDDA33
USB0_VDDA18
USB0_VDDA12 ⁽³⁾
AHCLKX0/AHCLKX2/USB_REFCLKIN/GP2[11]
PIN NO
PTP
TYPE⁽¹⁾ PULL⁽²⁾
DESCRIPTION
USB0 2.0 OTG
138
A
USB0 PHY data minus
137
A
USB0 PHY data plus
140
PWR
USB0 PHY 3.3-V supply
135
PWR
USB0 PHY 1.8-V supply input
134
PWR
USB0 PHY 1.2-V LDO output for bypass cap
125
I
IPD USB_REFCLKIN. Optional 48 MHz clock input.
(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.
Note: The pin type shown refers to the input, output or high-impedance state of the pin function when configured as the the signal name
highlighted in bold. All multiplexed signals may enter a high-impedance state when the configured function is input-only or the configured
function supports high-Z operation. All GPIO signals can be used as input or output. For multiplexed pins where functions have different
types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.
(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor
(3) Core power supply LDO output for USB PHY. This pin must be connected via a 0.22 -μF capacitor to VSS. When the USB peripheral is
not used, the USB_VDDA12 signal should still be connected via a 1-μF capacitor to VSS.
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