OMAPL137BPTPH Datasheet, PDF (183/205 Pages) Texas Instruments – Low-Power Applications Processor

OMAPL137-HT
www.ti.com
SPRS677B – FEBRUARY 2012 – REVISED FEBRUARY 2013
• Security
– Halting on a security violation (by cross-triggering via INTC)
– Memory accesses prevented to secure memory (this is ensured by system level security
mechanism)
• Program Trace
– Program flow corruption
– Code coverage
– Path coverage
– Thread/interrupt synchronization problems
• Data Trace
– Memory corruption
• Timing Trace
– Profiling
• Analysis Actions
– Stop program execution
– Control trace streams
– Generate debug interrupt
– Benchmarking with counters
– External trigger generation
– Debug state machine state transition
– Combinational and Sequential event generation
• Analysis Events
– Program event detection
– Data event detection
– External trigger Detection
– System event detection (i.e. cache miss)
– Debug state machine state detection
• Analysis Configuration
– Application access
– Debugger access
Category
Basic Debug
Table 5-105. ARM Debug Features
Hardware Feature
Software breakpoint
Hardware breakpoint
Availability
Unlimited
Up to 14 HWBPs, including:
2 precise ⁽¹⁾ HWBP inside ARM core which are shared
with watch points.
8 imprecise ⁽¹⁾ HWBPs from ETM’s address
comparators, which are shared with trace function, and
can be used as watch point too.
4 imprecise ⁽¹⁾ HWBPs from ICECrusher.
(1) Precise hardware breakpoints will halt the processor immediately prior to the execution of the selected instruction. Imprecise breakpoints
will halt the processor some number of cycles after the selected instruction depending on device conditions.
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Peripheral Information and Electrical Specifications 183
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