OMAPL137BPTPH Datasheet, PDF (198/205 Pages) Texas Instruments – Low-Power Applications Processor

OMAPL137-HT
SPRS677B – FEBRUARY 2012 – REVISED FEBRUARY 2013
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7.7 dMAX
Table 7-3 lists the dMAX control registers.
Register
Address
6000 0008h
6000 000Ch
6000 0010h
6000 0014h
6000 0018h
6000 001Ch
6000 0034h
6000 0054h
6000 0074h
6000 0094h
6000 0040h
6000 0060h
6000 0080h
6000 00A0h
-
-
Table 7-3. dMAX Control Registers
dMAX
Register
Name
DEPR
DEER
DEDR
DEHPR
DELPR
DEFR
DER0
DER1
DER2
DER3
DFSR0
DFSR1
DTCR0
DTCR1
DETR
DESR
Register Description
The dMAX event polarity register (DEPR) controls the polarity-rising edge (low
to high) or falling edge (high to low)-that sets the flag in the EFR register.
The events can be enabled by writing a 1 to dMAX Event Enable Register
(DEER).
The events can be disabled by writing a 1 to dMAX Event Disable Register
(DEDR).
An event is assigned to the high priority event group when the bit, which
corresponds to the event, is set in the dMAX Event High Priority Register
(DEHPR).
An event is assigned to the low priority event group when the bit, which
corresponds to the event, is set in the dMAX Event Low Priority Register
(DELPR).
The dMAX Event Flag Register (DEFR) indicates that an appropriate transition
edge (specified in the Event Polarity Register) has occurred on the event
signals. All events are captured in the event flag register, even when the
events are disabled.
The dMAX event register (DER0) reflects current value of the event signals 7-
0.
The dMAX event register (DER1) reflects current value of the event signals 15-
8.
The dMAX event register (DER2) reflects current value of the event signals 23-
16.
The dMAX event register (DER3) reflects current value of the event signals 31-
24.
dMAX FIFO status register 0. Writing a 1 to the DFSR0 register clears the
corresponding bit. Writing 0 has no effect.
dMAX FIFO status register 1. Writing a 1 to the DFSR1 register clears the
corresponding bit. Writing 0 has no effect.
dMAX transfer completion register 0. Writing a 1 to the DTCR0 register clears
the corresponding bit. Writing 0 has no effect.
dMAX transfer completion register 1. Writing a 1 to the DTCR1 register clears
the corresponding bit. Writing 0 has no effect.
dMAX event trigger register. By toggling a bit in this register the CPU can
trigger an event. To facilitate faster CPU access, the dMAX Event Trigger
Register is not memory-mapped and is placed inside the CPU module.
dMAX event status register. To facilitate low CPU access overhead this
register mirrors TCC bits from DTCR0 and DTCR1 registers. The register also
keeps track of dMAX controller activity. To facilitate faster CPU access, the
dMAX Event Status Register is not memory-mapped and is placed inside the
CPU module.
7.8 Key Manager
The Key Manager provides the management of the security keys within the Security Architecture. Its goal
as part of the architecture is to provide protection of keys / key information (known from this point on as
Keys) against unintended users.The following features are supported by the Key Manager:
• Controls the system level security key information
• Supports a configurable number of 128-bit security keys and 16-bit key checksums (up to 16)
• EFUSE scan chain snooping capabilities
– Device Type capture
– Security Key checksum validation
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