OMAPL137BPTPH Datasheet, PDF (126/205 Pages) Texas Instruments – Low-Power Applications Processor

OMAPL137-HT
SPRS677B – FEBRUARY 2012 – REVISED FEBRUARY 2013
www.ti.com
Table 5-64. Additional⁽¹⁾ SPI1 Master Timings, 5-Pin Option^{(2)(3) (4)} (continued)
NO.
22 t_{d(SCS_SPC)M}
23 t_{d(ENA_SPC)M}
Delay from SPI1_SCS
active to first
SPI1_CLK ^{(8) (9) (10)}
Delay from assertion of
SPI1_ENA low to first
SPI1_CLK edge.⁽¹¹⁾
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
Polarity = 0, Phase = 0,
to SPI1_CLK rising
Polarity = 0, Phase = 1,
to SPI1_CLK rising
Polarity = 1, Phase = 0,
to SPI1_CLK falling
Polarity = 1, Phase = 1,
to SPI1_CLK falling
MIN
2P -5
0.5t_c(SPC)M + 2P -5
2P -5
0.5t_c(SPC)M + 2P -5
MAX UNIT
ns
P+3
0.5t_c(SPC)M + P + 3
ns
P+3
0.5t_c(SPC)M + P + 3
(8) If SPI1_ENA is asserted immediately such that the transmission is not delayed by SPI1_ENA.
(9) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(10) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(11) If SPI1_ENA was initially deasserted high and SPI1_CLK is delayed.
Table 5-65. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Enable Option^{(2)(3) (4)}
NO.
Delay from final
24 t_{d(SPC_ENAH)S} SPI1_CLK edge to slave
deasserting SPI1_ENA.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
MIN
1.5 P -3
MAX UNIT
2.5 P + 19
– 0.5t_c(SPC)M + 1.5 P -3
1.5 P -3
– 0.5t_c(SPC)M + 2.5 P + 19
ns
2.5 P + 19
– 0.5t_c(SPC)M + 1.5 P -3 – 0.5t_c(SPC)M + 2.5 P + 19
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-61).
(2) Parameters are characterized from -40°C to 125°C unless otherwise noted.
(3) P = SYSCLK2 period
(4) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 5-66. Additional⁽¹⁾ SPI1 Slave Timings, 4-Pin Chip Select Option^{(2)(3) (4)}
NO.
25 t_{d(SCSL_SPC)S}
Required delay from SPI1_SCS asserted at slave to first
SPI1_CLK edge at slave.
Polarity = 0, Phase = 0,
from SPI1_CLK falling
26 t_{d(SPC_SCSH)S}
Required delay from final
SPI1_CLK edge before
SPI1_SCS is deasserted.
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
27
t_{ena(SCSL_SOMI)S}
Delay from master asserting SPI1_SCS to slave driving
SPI1_SOMI valid
28
t_{dis(SCSH_SOMI)S}
Delay from master deasserting SPI1_SCS to slave 3-stating
SPI1_SOMI
MIN
2P
0.5t_c(SPC)M + 2P+5
2P+5
0.5t_c(SPC)M + 2P+5
2P+5
(1) These parameters are in addition to the general timings for SPI slave modes (Table 5-61).
(2) Parameters are characterized from -40°C to 125°C unless otherwise noted.
(3) P = SYSCLK2 period
(4) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
MAX UNIT
ns
ns
P + 19 ns
P + 19 ns
126 Peripheral Information and Electrical Specifications
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