OMAPL137BPTPH Datasheet, PDF (1/205 Pages) Texas Instruments – Low-Power Applications Processor

OMAPL137-HT
www.ti.com
SPRS677B – FEBRUARY 2012 – REVISED FEBRUARY 2013
Low-Power Applications Processor
Check for Samples: OMAPL137-HT
1 Low-Power Applications Processor
1.1 Features
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• Highlights
– Bit-Field Extract, Set, Clear
– Dual Core SoC
– Normalization, Saturation, Bit-Counting
• 300-MHz ARM926EJ-S™ RISC MPU
– Compact 16-Bit Instructions
• 300-MHz C674x™ VLIW DSP
• C674x Two Level Cache Memory Architecture
– TMS320C674x Fixed/Floating-Point VLIW
– 32K-Byte L1P Program RAM/Cache
DSP Core
– 32K-Byte L1D Data RAM/Cache
– Enhanced Direct-Memory-Access Controller
– 256K-Byte L2 Unified Mapped RAM/Cache
3 (EDMA3)
– Flexible RAM/Cache Partition (L1 and L2)
– 128K-Byte RAM Shared Memory
– 1024KB L2 ROM
– Two External Memory Interfaces
• Enhanced Direct-Memory-Access Controller 3
– Two External Memory Interfaces Modules
(EDMA3):
– LCD Controller
– 2 Transfer Controllers
– Two Serial Peripheral Interfaces (SPI)
– 32 Independent DMA Channels
– Multimedia Card (MMC)/Secure Digital (SD)
– 8 Quick DMA Channels
– Two Master/Slave Inter-Integrated Circuit
– Programmable Transfer Burst Size
– One Host-Port Interface (HPI)
• TMS320C674x™ Fixed/Floating-Point VLIW DSP
– USB 1.1 OHCI (Host) With Integrated PHY
Core
(USB1)
– Load-Store Architecture With Non-Aligned
• Applications
Support
– Industrial Diagnostics
– 64 General-Purpose Registers (32 Bit)
– Test and measurement
– Six ALU (32-/40-Bit) Functional Units
– Military Sonar/Radar
– Medical measurement
– Professional Audio
– Down Hole Industry
• Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
• ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
• Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Additions Per
Clock, Four DP Additions Every 2 Clocks
• Supports up to Two Floating Point (SP or
DP) Approximate Reciprocal or Square
Root Operations Per Cycle
– Two Multiply Functional Units
• Mixed-Precision IEEE Floating Point
Multiply Supported up to:
– Single Cycle MAC
– ARM^® Jazelle^® Technology
– 2 SP x SP -> SP Per Clock
– 2 SP x SP -> DP Every Two Clocks
– EmbeddedICE-RT™ for Real-Time Debug
– 2 SP x DP -> DP Every Three Clocks
• ARM9 Memory Architecture
– 2 DP x DP -> DP Every Four Clocks
• C674x Instruction Set Features
• Fixed Point Multiply Supports Two 32 x
– Superset of the C67x+™ and C64x+™ ISAs
32-Bit Multiplies, Four 16 x 16-Bit
– Up to 3648/2736 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
1
Multiplies, or Eight 8 x 8-Bit Multiplies per
Clock Cycle, and Complex Multiples
– Instruction Packing Reduces Code Size
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DSP/BIOS, C67x+, C64x+, TMS320C6000, C6000 are trademarks of Texas Instruments.
2
ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited.
3
ARM, Jazelle are registered trademarks of ARM Limited.
4
Windows is a registered trademark of Microsoft Corporation.
5
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated