OMAPL137BPTPH Datasheet, PDF (101/205 Pages) Texas Instruments – Low-Power Applications Processor

OMAPL137-HT
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SPRS677B – FEBRUARY 2012 – REVISED FEBRUARY 2013
5.15.1 McASP Peripheral Registers Description(s)
Registers for the McASP are summarized in Table 5-42. The registers are accessed through the
peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can
also be accessed through the DMA port, as listed in Table 5-43
Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 5-44. Note that the AFIFO Write
FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control
registers are accessed through the peripheral configuration port. See the TMS320C674x/OMAP-L1x
Processor Peripherals Overview Reference Guide. – Literature Number SPRUFK9 for more details.
Offset
0h
10h
14h
18h
1Ch
1Ch
20h
44h
48h
4Ch
50h
60h
64h
68h
6Ch
70h
74h
78h
7Ch
80h
84h
88h
8Ch
ACh
A4h
A8h
ACh
B0h
B4h
B8h
BCh
C0h
C4h
Table 5-42. McASP Registers Accessed Through Peripheral Configuration Port
McASP0
BYTE
ADDRESS
0x01D0 0000
0x01D0 0010
0x01D0 0014
0x01D0 0018
0x01D0 001C
0x01D0 001C
McASP1
BYTE
ADDRESS
0x01D0 4000
0x01D0 4010
0x01D0 4014
0x01D0 4018
0x01D0 401C
0x01D0 401C
McASP2
BYTE
ADDRESS
0x01D0 8000
0x01D0 8010
0x01D0 8014
0x01D0 8018
0x01D0 801C
0x01D0 801C
Acronym
REV
PFUNC
PDIR
PDOUT
PDIN
PDSET
0x01D0 0020
0x01D0 0044
0x01D0 0048
0x01D0 004C
0x01D0 0050
0x01D0 0060
0x01D0 4020
0x01D0 4044
0x01D0 4048
0x01D0 404C
0x01D0 4050
0x01D0 4060
0x01D0 8020
0x01D0 8044
0x01D0 8048
0x01D0 804C
0x01D0 8050
0x01D0 8060
PDCLR
GBLCTL
AMUTE
DLBCTL
DITCTL
RGBLCTL
0x01D0 0064
0x01D0 0068
0x01D0 006C
0x01D0 0070
0x01D0 0074
0x01D0 0078
0x01D0 007C
0x01D0 0080
0x01D0 0084
0x01D0 0088
0x01D0 008C
0x01D0 00A0
0x01D0 4064
0x01D0 4068
0x01D0 406C
0x01D0 4070
0x01D0 4074
0x01D0 4078
0x01D0 407C
0x01D0 4080
0x01D0 4084
0x01D0 4088
0x01D0 408C
0x01D0 40A0
0x01D0 8064
0x01D0 8068
0x01D0 806C
0x01D0 8070
0x01D0 8074
0x01D0 8078
0x01D0 807C
0x01D0 8080
0x01D0 8084
0x01D0 8088
0x01D0 808C
0x01D0 80A0
RMASK
RFMT
AFSRCTL
ACLKRCTL
AHCLKRCTL
RTDM
RINTCTL
RSTAT
RSLOT
RCLKCHK
REVTCTL
XGBLCTL
0x01D0 00A4
0x01D0 00A8
0x01D0 00AC
0x01D0 00B0
0x01D0 00B4
0x01D0 00B8
0x01D0 00BC
0x01D0 00C0
0x01D0 00C4
0x01D0 40A4
0x01D0 40A8
0x01D0 40AC
0x01D0 40B0
0x01D0 40B4
0x01D0 40B8
0x01D0 40BC
0x01D0 40C0
0x01D0 40C4
0x01D0 80A4
0x01D0 80A8
0x01D0 80AC
0x01D0 80B0
0x01D0 80B4
0x01D0 80B8
0x01D0 80BC
0x01D0 80C0
0x01D0 80C4
XMASK
XFMT
AFSXCTL
ACLKXCTL
AHCLKXCTL
XTDM
XINTCTL
XSTAT
XSLOT
Register Description
Revision identification register
Pin function register
Pin direction register
Pin data output register
Read returns: Pin data input register
Writes affect: Pin data set register (alternate write
address: PDOUT)
Pin data clear register (alternate write address: PDOUT)
Global control register
Audio mute control register
Digital loopback control register
DIT mode control register
Receiver global control register: Alias of GBLCTL, only
receive bits are affected - allows receiver to be reset
independently from transmitter
Receive format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
Receive high-frequency clock control register
Receive TDM time slot 0-31 register
Receiver interrupt control register
Receiver status register
Current receive TDM time slot register
Receive clock check control register
Receiver DMA event control register
Transmitter global control register. Alias of GBLCTL,
only transmit bits are affected - allows transmitter to be
reset independently from receiver
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
Transmit high-frequency clock control register
Transmit TDM time slot 0-31 register
Transmitter interrupt control register
Transmitter status register
Current transmit TDM time slot register
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