AMC7823 Datasheet, PDF (39/48 Pages) Texas Instruments – ANALOG MONITORING AND CONTROL CIRCUIT

AMC7823
www.ti.com
DAC Configuration Register (Read/Write)
Bit 15
MSB
SLDA7
Bit 14
SLDA6
Bit 13
SLDA5
Bit 12
SLDA4
Bit 11
SLDA3
Bit 10
SLDA2
Bit 9
SLDA1
Bit 8
SLDA0
SLAS453A – APRIL 2005 – REVISED OCTOBER 2005
Bit 7
GDAC7
Bit 6
GDAC6
Bit 5
GDAC5
Bit 4
GDAC4
Bit 3
GDAC3
Bit 2
GDAC2
Bit 1
GDAC1
Bit 0
LSB
GDAC0
SLDA-n DAC Synchronous Load Enable bit.
SLDA-n = 1: Synchronous Load enabled. When the synchronous load DAC signal occurs, DAC-n
Latch is loaded with the value of the corresponding DAC-n Data Register, and the output of
DAC-n is updated immediately. This load signal can be the rising edge of the external signal
ELDAC or the internal load signal ILDAC. Writing the data word 0xBB00 into the LOAD DAC
Register generates ILDAC. A write command to the DAC-n Data Register updates that register
only, and does not change the DAC-n output.
SLDA-n = 0: Asynchronous Load enabled. A write command to the DAC-n Data Register
immediately updates DAC-n Latch and the output of DAC-n. The synchronous load DAC signal
(ILDAC or ELDAC) does not affect DAC-n.
GDAC-n DAC-n Output Buffer Amplifier Gain bit.
GDAC-n = 1: The gain of the DAC-n output buffer amplifier is equal to 2.
GDAC-n = 0: The gain of the DAC-n output buffer amplifier is equal to 1.
The combination of the bit GDAC-n and the reference voltage (internal or external) sets the full-scale range of
each DAC-n.
Table 11 describes the full-scale DAC output range as a function of bits SREF, GREF and GDAC-n.
Table 11. Full-Scale DAC Output Range
SREF
0
0
0
0
1
1
GREF
0
0
1
1
Don't
care
Don't
care
GDAC-n
0
1
0
1
0
1
REFERENCE
Internal 1.25 V
Internal 1.25 V
Internal 2.5 V
Internal 2.5 V
External V_REF
External V_REF
OUTPUT RANGE
AV_DD = 3 V
0 V to 1.25 V
AV_DD = 5 V
0 V to 1.25 V
0 V to 2.50 V
0 V to 2.50 V
0 V to 2.50 V
0 V to 2.50 V
Saturated at 3 V
0 V to 5.00 V
0 V to External V_REF,
External V_REF ≤ AV_DD
0 V to External V_REF × 2
2 × External V_REF ≤ AV_DD
0 V to External V_REF,
External V_REF ≤ AV_DD
0 V to External V_REF × 2
2 × External V_REF ≤ AV_DD
When an external reference is applied, the full-scale output range of DAC-n is equal to V_REF for GDAC = 0, and
equal to 2 x V_REF for GDAC-n = 1.
To avoid saturation, the full-scale output range of DAC-n must not be greater than AV_DD. After power-on or reset,
all bits are cleared to '0'.
Load DAC Register (Read/Write)
Bit 15
MSB
1
Bit 14
0
Bit 13
1
Bit 12
1
Bit 11
1
Bit 10
0
Bit 9
1
Bit 8
1
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
LSB
0
The data word 0xBB00 (shown above) written into the LOAD DAC Register generates ILDAC, the internal load
DAC signal. ILDAC and the external ELDAC signal work in a similar manner. ILDAC shifts data from the DAC-n
Data register to the DAC-n Latch and updates the output for all DAC-n with the corresponding SLDA-n bit set to
'1'. Other codes written to this register do not generate ILDAC and have no impact on any DAC-n. The LOAD
DAC Register is cleared after ILDAC is generated. The register is also cleared after power-on or reset.
39