AMC7823 Datasheet, PDF (30/48 Pages) Texas Instruments – ANALOG MONITORING AND CONTROL CIRCUIT

AMC7823
SLAS453A – APRIL 2005 – REVISED OCTOBER 2005
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After power-on or reset, all DAC-n Data Registers and all DAC-n Latches are cleared to '0'. This clearing process
results in all DAC outputs at 0 V, gain of unity, and a full-scale output range preset to either 1.25 V or equal to
the external reference (if it is applied) because bits SREF and GREF are also cleared to '0'.
Zero Code Output Value
Each DAC buffer is clamped to prevent the output from going to 0 V. Thus, when the input code is 000h, the
output is typically 15 mV to 20 mV. This output keeps the closed-loop DAC output buffer in an active, stable
operating regime, allowing it to immediately respond to an input that produces an output typically greater than
20 mV. Near-zero-volt output for a particular DAC-n may be achieved by clearing bit PDAC-n to '0' in the
Power-Down register.
POWER-DOWN MODE
The AMC7823 is implemented with power-down mode. Bits in the Power-Down Register control power applied to
the ADC, each DAC output buffer, the output amplifier of the precision current source, and the reference buffer.
The reference buffer drives all the DAC resistor strings and supplies reference voltage to the precision current
source. After power-on reset or any forced hardware or software reset, the Power-Down Register is cleared, and
all these specified components are in power-down mode.
In power-down mode, most of the linear circuitry is shut down. The ADC halts conversions, output current of the
precision current source drops to zero, and each external DAC output pin is switched from the DAC output buffer
to analog ground through an internal 5-kΩ resistor. The internal reference and the internal oscillator remain
powered to facilitate rapid recovery from power-down mode.
None of the bits in the Power-Down Register affect the digital logic. All digital signals (such as the SPI interface,
RESET, ELDAC, ALR, and all GPIO) still work normally in any power-down condition. In power-down mode, the
host can read registers to get information, or write to registers to change settings. No write operation can start
the ADC (if the ADC is in power-down), or change the DAC output (if the DAC is in power-down), but write
operations can update register values. The new register values are effective immediately upon exiting the
power-down mode. In this way, the host can preset DACs and the ADC before a wake-up call.
The contents of all Page 1 addresses (see Table 2) do not change when entering or exiting power-down mode.
The contents of the ADC registers and the alarm information in the ALR and GPIO Registers of Page 0 do not
change when entering or exiting power-down mode if the ADC is in direct mode before powering down. To
avoid losing ADC register content and alarm information in the ALR and GPIO Registers while the ADC is
powered down, do not issue a convert command during power-down mode. General-purpose I/O data are not
affected. For details, see the sections on the ALR Register and the GPIO Register.
For power-down mode details, see the Power-Down Register section.
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