AMC7823 Datasheet, PDF (26/48 Pages) Texas Instruments – ANALOG MONITORING AND CONTROL CIRCUIT

AMC7823
SLAS453A – APRIL 2005 – REVISED OCTOBER 2005
www.ti.com
The bit GREF in the AMC Status/Configuration Register selects between two preset internal reference values.
When GREF = 0 (power-up default condition), the internal reference is set to 1.25 V. When GREF = 1, the
internal reference is 2.5 V. GREF must be cleared to '0' when the power supply is less than 5 V.
When an external reference is applied, the input range is 0 to 2 × V_REF, and is not affected by the bit GREF. In
this case, ideally SREF has been set to '1' and the internal reference is disconnected. This condition is preferred
for operating the AMC7823. If SREF = 0, the external reference overrides the internal reference, provided it can
accommodate a 10-kΩ load. To avoid input saturation, the external reference must not be greater than 2.5 V
when the analog power supply is 5 V, and must not be greater than 1.25 V when the supply is 3 V.
Figure 45 illustrates the ADC operation.
New ADC Conversion Trigger
Clear DAVF bit in AMC
Status/Configuration Register
Clear all ALR-n in ALR Register
Set [ADR] = [SA]
(1)
Sample
Convert
Update ADC-n TMPRY Register
No
First four channels?
Yes
Out-of-range?
No
[ADR] + 1
(2)
Drive GALR Pin Low
Yes
Set ALR-n Bit in ALR Register
No
Direct-Mode
(1)
[ADR] > [EA] ?
Yes
Update ADC-n
Data Register
Auto-Mode
No
Set DAVF bit;
Drive DAV Pin Low
Yes
(3)
Auto-Mode,
Internal Trigger only
(4)
Apply 2-ms Pulse (Low)
to Pin DAV
ADC in idle
Waiting new trigger
(1) [SA] represents the first input channel, [EA] represents the last input channel. [ADR] represents the current input
channel. [SA3:SA0] is the address of [SA]. [EA3:EA0] is the address of [EA].
(2) GALR pin goes high and bits ALR-n are cleared after new ADC Conversion trigger.
(3) After reading the ADC Data Register, bit DAVF is cleared, and the DAV pin goes high.
(4) In Auto-mode, bit DAVF is always cleared.
Figure 45. ADC Operation Flow Chart
26