AMC7823 Datasheet, PDF (28/48 Pages) Texas Instruments – ANALOG MONITORING AND CONTROL CIRCUIT

AMC7823
SLAS453A – APRIL 2005 – REVISED OCTOBER 2005
www.ti.com
DAC OPERATION (see DAC-n Data Registers and DAC Configuration Register)
AMC7823 has eight double-buffered DACs. The outputs of the DACs can be updated synchronously or
individually (asynchronously). Figure 47 illustrates the generic DAC structure.
Data to Host
when Read
DAC-0
Data from
Host
DAC-0
Data
Bit SLDA-n of DAC Configuration Register determines
when DAC-n Latch is loaded with the value of
DAC-n Data Register.
SLDA-n = 1: Latch is loaded when Synchronous
Loading signal occurs; synchronous loading
SLDA-n = 0: Latch is loaded immediately after
DAC-n Data register is written; asynchronous loading
DAC-0
Latch
V_OUT0
V_OUT Range: 0 - V_REF x Gain
5 kW
Bit PDAC-0
(Power-Down bit in Power-Down
Register; see (1) )
Gain = 2 if GDAC-0 = 1
Gain = 1 if GDAC-0 = 0
Bit GDAC-0
(DAC Configuration Register)
DAC-7
Data
DAC-7
Bit PDAC-7 (Power-Down bit
in Power-Down Register)
BB00h
Load DAC ^{Internal ILDAC}
Register
External ELDAC
Synchronous
Loading Signal
Bit GDAC−7
Loads all DAC-n latches when corresponding SLDA-n is set to ‘1’.
Does not affect DAC-n when SLDA-n is cleared to ‘0’.
(1) When PDAC-n = 0, DAC-n is in power-down mode; the output buffer of DAC-n connects to ground through a 5-kΩ
load.
Figure 47. DAC Structure
Double-Buffered Data Register
All eight DAC data registers are double-buffered. Each DAC has an internal latch preceded by an input register.
Data is initially written to an individual DAC-n Data register and then transferred to its corresponding DAC-n
Latch. When the DAC-n Latch is updated, the output of DAC-n changes to the newly set value. When the host
reads the register memory map location labeled DAC-n Data, the value held in the DAC-n Latch is returned (not
the value held in the input DAC-n Data Register).
Synchronous Load, Asynchronous Load, and Output Updating
The DAC latches can be updated synchronously or asynchronously. The bit SLDA-n (Synchronous Load) of the
DAC Configuration Register is used to specify the DAC updating mode.
Asynchronous mode is active when SLDA-n is cleared to '0'. Immediately after writing to the DAC-n Data
Register, its data is transferred to the corresponding DAC-n Latch Register, and the output of DAC-n changes
accordingly.
Synchronous mode is selected when the bit SLDA-n is set to '1'. The value of the DAC-n Data Register is
transferred to the DAC-n Latch only after an active DAC synchronous loading signal occurs, which immediately
updates the DAC-n output. Under synchronous loading operation, writing data into a DAC-n Data Register
changes only the value in that register, but not the content of DAC-n Latch nor the output of DAC-n, until the
synchronous load signal occurs.
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