AMC7823 Datasheet, PDF (24/48 Pages) Texas Instruments – ANALOG MONITORING AND CONTROL CIRCUIT

AMC7823
SLAS453A – APRIL 2005 – REVISED OCTOBER 2005
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Conversion Mode
When internal trigger mode is selected (ECNVT = 0), two types of ADC conversion are available: direct-mode
and auto-mode. The bit CMODE (Conversion MODE) of the ADC Control Register specifies the conversion
mode. When external trigger mode is selected (ECNVT = 1), only direct-mode conversion is available. In this
case, bit CMODE in the ADC Control Register is ignored. (See Table 3.)
In direct-mode, each analog channel within the specified group is converted a single time. After the last channel
is converted, the ADC goes into idle state and waits for a new trigger. Only the starting channel is converted if
the ending address is equal to or smaller than the starting address.
Auto-mode is a continuous operation. In auto-mode, each analog channel within the specified group is converted
sequentially from [SA3:SA0] to [EA3:EA0] and repeatedly until one of the following events occur:
• a new internal trigger is issued;
• the conversion mode is changed to direct-mode by rewriting the ADC Control Register; or
• the external trigger is enabled by rewriting the AMC Status/Configuration Register.
When a new internal trigger is issued, a new conversion process starts. If the ending address [EA3:EA0] is equal
to or smaller than the starting address [SA3:SA0], the starting address channel is repeatedly converted and
others are ignored.
Table 3 summarizes the ADC conversion modes.
ECNVT OF AMC STATUS/
CONFIGURATION REGISTER
1
0
0
Table 3. ADC Conversion Mode
CMODE OF
ADC CONTROL REGISTER
–
0
1
ADC CONVERSION MODE
External Trigger, Direct-Mode
Internal Trigger, Direct-Mode
Internal Trigger Auto-Mode
Double-Buffered ADC Data Register
The host can access all nine double-buffered ADC Data registers. The conversion result from the analog input
with the channel address n is stored in the ADC-n Data register. When the conversion of an individual channel is
completed, the data is immediately transferred into the corresponding ADC-n temporary (TMPRY) register, the
first stage of the data buffer. When the conversion of the last channel ( [EA3:EA0] ) finishes, all data in ADC-n
TMPRY registers are transferred simultaneously into the corresponding ADC-n Data registers, the second stage
of the data buffer. However, if a data transfer is in progress between an ADC-n Data Register and the AMC Shift
Register, this ADC-n Data Register is not updated until the data transfer is complete. The conversion result from
channel address n is stored in the ADC-n Data Register. For example, the result from channel [0x04] is stored in
the ADC-4 Data Register, and the result from channel [0x07] is stored in the ADC-7 Data Register. The ADC-8
Data Register is used to store on-chip temperature measurement data (see the On-chip Temperature Sensor).
SCLK Clock Noise
The host activates the slave select signal SS (low) to access the AMC7823. When SS is high, the SCLK clock is
blocked. To avoid noise caused by SCLK clock, deactivate SS (high) for at least the conversion process time
immediately after the ADC conversion starts.
Handshaking with the Host (see AMC Status/Configuration Register)
The DAV pin and the bit DAVF (Data Available Flag) of the AMC Status/Configuration Register provide
handshaking with the host. Pin and bit status depend on the conversion mode (direct or auto). In direct-mode,
after ADC-n Data registers of all of the selected channels are updated, the DAVF bit in the AMC
Status/Configuration Register is set immediately to '1', and the DAV pin is active (low) to signify new data is
available. Reading the ADC-n Data Register or re-starting the ADC clears bit DAVF to '0' and deactivates DAV
pin (high).
In auto-mode, after ADC-n Data registers of the selected channels are updated, a pulse of 2 µs (low) appears on
pin DAV to signify new data is available. However, bit DAVF is always cleared to '0' in auto-mode.
Figure 42, Figure 43 and Figure 44 illustrate the handshaking protocol.
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