AMC7823 Datasheet, PDF (36/48 Pages) Texas Instruments – ANALOG MONITORING AND CONTROL CIRCUIT

AMC7823
SLAS453A – APRIL 2005 – REVISED OCTOBER 2005
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The value in the Threshold-Hi-n Register defines the upper bound threshold of the nth analog input, while the
value in Threshold-Low-n defines the lower bound. These two bounds specify a window for the out-of-range
detection. The out-of-range condition occurs when the input is set outside the window defined by these
boundaries. To implement single upper-bound threshold detection, the host processor can set the upper bound
to the desired value and the lower bound to zero. For lower-bound detection, the host can set the lower bound to
the desired value and the upper bound to the full-scale input.
To deactivate the alarm function (ALR-n always '0'), set the threshold registers to their default values as specified
in Table 2.
Note: The value of Threshold-Hi-n must not be less than the value of Threshold-Low-n; otherwise, ALR-n is
always set to '1' and the alarm indicator is always active.
If any out-of-range alarm occurs, the Global Alarm pin (GALR, pin 1) goes logic low. This function provides an
interrupt to the host so that it may query the ALR Register (alarm register) to determine which channels are
out-of-range.
The general-purpose I/O pins, GPIO-0, GPIO-1, GPIO-2 and GPIO-3, are dual-purpose and can be configured
as individual out-of-range alarm indicators denoted as ALR-0, ALR-1, ALR-2 and ALR-3 as discussed previously.
Each ALR-n pin displays the logical complement of of each corresponding ALR-n bit. For example, when an
alarm condition occurs, bit ALR-n is set to '1' and pin ALR-n goes logic low. For each GPIO-n pin configured as
an alarm, its corresponding IOST-n bit in the GPIO Register displays the complement of bit ALR-n. For example,
when bit ALR-n is set to '1', bit IOST-n is cleared to '0'. (Note that pins GPIO-4 and GPIO-5 are not dual-purpose,
and are general digital I/O pins only.)
CLEARING ALARM INDICATORS
In summary, the maximum alarm condition would have pin GALR (pin 1) and one or more pins ALR-n at logic
low, one or more bits IOST-n cleared to '0', and one or more bits ALR-n set to '1'. All of these remain in alarm
status until the alarm-causing conditions are removed and a new conversion is completed. When the ADC is
operating in auto-mode, the alarm indicators are displayed after the first 2-µs pulse on pin DAV following
detection of one or more of the first four input channels out-of-range. The selected group of input channels is
converted repeatedly and the alarm indicators remain constant until the offending inputs are corrected or until the
threshold window levels are adjusted. When the alarm-causing conditions are removed, the alarm indicators are
cleared after the first 2-µs pulse on DAV following removal.
When the ADC is operating in direct-mode, the alarm indicators are displayed after the first data valid signal
(DAV, pin 2, at logic low) following an out-of-range condition. The alarm indicators remain constant until either
the inputs are corrected or the threshold windows adjusted, and another convert command is issued and
completed.
In either operating mode, the alarm indicators may be cleared if a new conversion command is issued identifying
a subset of input channels not containing the channel or channels out of range.
The alarm indicators may also be cleared by a general hardware or software reset, or a power-on reset.
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