DS125RT410 Datasheet, PDF (35/42 Pages) Texas Instruments – DS125RT410 Low Power Multi-Rate Quad Channel Retimer

DS125RT410
www.ti.com
SNLS459 – APRIL 2011
The reference clock mode is set by a two-bit field, register 0x36, bits 5:4. This field should always be set to a
value of 3 or 2'b11.
A 25 MHz reference clock signal must be provided on the reference in pin (pin 19). The use of the reference
clock in the DS125RT410 is explained below.
First, the reference clock allows the DS125RT410 to calibrate its VCO frequency at power-up and upon reset.
This enables the DS125RT410 to determine the optimum coarse VCO tuning setting a-priori, which makes phase
lock much faster. The DS125RT410 is not required to tune through the available coarse VCO tuning settings as it
tries to acquire lock to an input signal. It can select the correct setting immediately.
Second, if the DS125RT410 loses lock for some reason and the VCO drifts from its phase-locked frequency, the
DS125RT410 can detect this very quickly using the reference clock. Detecting an out-of-lock condition quickly
allows the DS125RT410 to raise an interrupt indicating that it has lost lock quickly, which the system controller
can then service to correct the problem quickly.
Finally, some data signals with large jitter spurs in their frequency spectra can cause the DS125RT410 to false
lock. This occurs when the data pattern exhibits strong discrete frequency components in its frequency spectrum,
or when the data pattern has a lot of periodic jitter imposed on it. If you look at such a signal in the frequency
domain using a spectrum analyzer, it will clearly show “spurs” close in to the fundamental data rate frequency.
These spurs can cause the DS125RT410 to false lock.
Using the 25 MHz reference clock, the DS125RT410 can detect when it is locked to a jitter spur. When this
happens, the DS125RT410 will re-initiate the adaptation and lock sequence until it locks to the correct data rate.
This provides immunity to false lock conditions.
Overriding the CTLE Settings Used for CTLE Adaptation
Register 0x2c, bits 3:0, Register 0x2f, bit 3, Register 0x39, bits 4:0, and Registers 0x50-0x5f
The CTLE adaptation algorithm operates by setting the CTLE boost stage controls to a set of pre-determined
boost settings, each of which provides progressively more high-frequency boost. At each stage in the adaptation
process, the DS125RT410 attempts to phase lock to the equalized signal. If the phase lock succeeds, the
DS125RT410 measures the horizontal and vertical eye openings using the internal eye monitor circuit. The
DS125RT410 computes a figure of merit for the eye opening and compares it to the previous best value of the
figure of merit. While the figure of merit continues to improve, the DS125RT410 continues to try additional values
of the CTLE boost setting until the figure of merit ceases to improve and begins to degrade. When the figure of
merit starts to degrade, the DS125RT410 still continues to try additional CTLE settings for a pre-determined trial
count called the “look-beyond” count, and if no improvement in the figure of merit results, it resets the CTLE
boost values to those that produced the best figure of merit. The resulting CTLE boost values are then stored in
register 0x03. The “look-beyond” count is configured by the value in register 0x2c, bits 3:0. The value is 0x2 by
default.
The set of boost values used as candidate values during CTLE adaptation are stored as bit fields in registers
0x40-0x5f. The default values for these settings are shown in Table 14. These values may be overridden by
setting the corresponding register values over the SMBus. If these values are overridden, then the next time the
CTLE adaptation is performed the set of CTLE boost values stored in these registers will be used for the
adaptation. Resetting the channel registers by setting bit 2 of channel register 0x00 will reset the CTLE boost
settings to their defaults. So will power-cycling the DS125RT410.
Copyright © 2011, Texas Instruments Incorporated
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