DS125RT410 Datasheet, PDF (25/42 Pages) Texas Instruments – DS125RT410 Low Power Multi-Rate Quad Channel Retimer

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Address (Hex)
0x33
0x36
0x39
0x3a
0x3e
0x40 – 0x5f
0x6a
0x6b
0x6c
0x6d
0x6e
0x70
DS125RT410
SNLS459 – APRIL 2011
Table 7. Channel Registers (continued)
Bits
Default Value (Hex) Mode
7:4
0x8
R/W
3:0
0x8
R/W
6
0x0
R/W
5:4
0x3
R/W
2
0x0
R/W
1:0
0x1
R/W
4:0
0x0
R/W
7:6
0x2
R/W
5:4
0x2
R/W
3:2
0x1
R/W
1:0
0x1
R/W
7
0x1
R/W
CTLE Settings for Adaptation – see Table 14
7:4
0x4
R/W
3:0
0x4
R/W
7:0
0x0
R/W
7:0
0x0
R/W
7:0
0x0
R/W
7
0x0
R/W
2:0
0x3
R/W
Field Name
Description
heo_thresh[3:0]
HEO Threshold for
CTLE Adaptation
Handoff
veo_thresh[3:0]
VEO Threshold for
CTLE Adaptation
Handoff
heo_veo_int_enable Enable HEO/VEO
Interrupt
ref_mode[1:0]
Reference Clock
Mode <1:0>
mr_cdr_cap_dac_rng Enable Override for
_ov
VCO Cap DAC
Range
mr_cdr_cap_dac_rng[ Cap DAC Range
1:0]
<1:0>
start_index[4:0]
Start Index for CTLE
Adaptation <4:0>
(Enable from Register
0x2f, Bit 3)
fixed_eq_BST0[1:0]
Fixed CTLE Stage 0
Boost Setting for
Lower Data Rates
<1:0>
fixed_eq_BST1[1:0]
Fixed CTLE Stage 1
Boost Setting for
Lower Data Rates
<1:0>
fixed_eq_BST2[1:0]
Fixed CTLE Stage 2
Boost Setting for
Lower Data Rates
<1:0>
fixed_eq_BST3[1:0]
Fixed CTLE Stage 3
Boost Setting for
Lower Data Rates
<1:0>
HEO_VEO_LOCKMO Enable HEO/VEO
N_EN
Lock Monitoring
veo_lck_thrsh[3:0]
heo_lck_thrsh[3:0]
fom_a[7:0]
fom_b[7:0]
fom_c[7:0]
en_new_fom_ctle
eq_lb_cnt[2:0]
Vertical Eye Opening
Lock Threshold <3:0>
Horizontal Eye
Opening Lock
Threshold <3:0>
Adaptation Figure of
Merit Term a<7:0>
Adaptation Figure of
Merit Term b<7:0>
Adaptation Figure of
Merit Term c<7:0>
Enable Alternate
Figure of Merit for
CTLE Adaptation
CTLE Adaptation
Look-Beyond Count
<2:0>
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