DS125RT410 Datasheet, PDF (26/42 Pages) Texas Instruments – DS125RT410 Low Power Multi-Rate Quad Channel Retimer

DS125RT410
SNLS459 – APRIL 2011
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Resetting Individual Channels of the Retimer
Register 0x00, bit 2, and register 0x0a, bits 3:2
Bit 2 of channel register 0x00 are used to reset all the registers for the corresponding channel to their factory
default settings. This bit is self-clearing. Writing this bit will clear any register changes you have made in the
DS125RT410 since it was powered-up.
To reset just the CDR state machine without resetting the register values, which will re-initiate the lock and
adaptation sequence for a particular channel, use channel register 0x0a. Set bit 3 of this register to enable the
reset override, then set bit 2 to force the CDR state machine into reset. These bits can be set in the same
operation. When bit 2 is subsequently cleared, the CDR state machine will resume normal operation. If a signal
is present at the input to the selected channel, the DS125RT410 will attempt to lock to it and will adapt its CTLE.
Interrupt Status
Control/Shared Register 0x05, bits 3:0, Register 0x01, bits 4 and 0, Register 0x30, bit 4, Register 0x32, and
Register 0x36, bit 6
Each channel of the DS125RT410 will generate an interrupt under several different conditions. The DS125RT410
will always generate an interrupt when it loses CDR lock or when a signal is no longer detected at its input. If the
HEO/VEO interrupt is enabled by setting bit 6 of register 0x36, then the retimer will generate an interrupt when
the horizontal or vertical eye opening falls below the preset values even if the retimer remains locked. When one
of these interrupt conditions occurs, the retimer alerts the system controller via hardware and provides additional
details via register reads over the SMBus.
First, the open-drain interrupt line INT is pulled low. This indicates that one or more of the channels of the retimer
has generated an interrupt. The interrupt lines from multiple retimers can be wire-ANDed together so that if any
retimer generates an interrupt the system controller can be notified using a single interrupt input.
if the interrupt has occurred because the horizontal or vertical eye opening has dropped below the pre-set
threshold, which is set in channel register 0x32, then bit 4 of register 0x30 will go high. This indicates that the
source of the interrupt was the HEO or VEO.
If the interrupt has occurred because the CDR has fallen out of lock, or because the signal is no longer detected
at the input, then bit 4 and/or bit 0 of register 0x01 will go high, indicating the cause of the interrupt.
In either case, the control/shared register set will indicate which channel caused the interrupt. This is read from
bits 3:0 of control/shared register 0x05.
When an interrupt is detected by the controller on the interrupt input, the controller should take the following
steps to determine the cause of the interrupt and clear it.
1. The controller detects the interrupt by detecting that the INT line has been pulled low by one of the retimers
to which it is connected.
2. The controller reads control/shared register 0x05 from all the DS125RT410s connected to the INT line. For at
least one of these devices, at least one of the bits 3:0 will be set in this register.
3. For each device with a bit set in bits 3:0 of control/shared register 0x05, the controller determines which
channel or channels produced an interrupt. Refer to Table 5 for a mapping of the bits in this bit field to the
channel producing the interrupt.
4. When the controller detects that one of the retimers has a 1 in one of the four LSBs of this register, the
controller selects the channel register set for that channel of that retimer by writing to the channel select
register, 0xff, as previously described.
5. For each channel that generated an interrupt, the controller reads channel register 0x01. If bit 4 of this
register is set, then the interrupt was caused by a loss of CDR lock. If bit 0 is set, then the interrupt was
caused by a loss of signal. it is possible that both bits 0 and 4 could be set. Reading this register will clear
these bits.
6. Optionally, for each channel that generated an interrupt, the controller reads channel register 0x30. If bit 4 of
this register is set, then the interrupt was caused by HEO and/or VEO falling out of the configured range.
This interrupt will only occur if bit 6 of channel register 0x36 is set, enabling the HEO/VEO interrupt. Reading
register 0x30 will clear this interrupt bit.
7. Once the controller has determined what condition caused the interrupt, the controller can then take the
appropriate action. For example, the controller might reset the CDR to cause the retimer to re-adapt to the
incoming signal. If there is no longer an incoming signal (indicated by a loss of signal interrupt, bit 0 of
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