DS125RT410 Datasheet, PDF(33/42 Page) Texas Instruments – DS125RT410 Low Power Multi-Rate Quad Channel Retimer

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DS125RT410 Datasheet, PDF (33/42 Pages) Texas Instruments – DS125RT410 Low Power Multi-Rate Quad Channel Retimer

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DS125RT410

www.ti.com

SNLS459 â APRIL 2011

7. Read the data array from the DS125RT410. This can be accomplished in two ways.

â If you are using multi-byte reads, address the DS125RT410 to read from register 0x25. Continue to read

from this register without addressing the device again until you have read all the data desired. The

read operation can be interrupted by addressing the device again and then resumed by reading once

again from register 0x25.

â If you are not using multi-byte reads, then read the MSB for each phase and amplitude offset setting from

time you want to read a new byte.

8. In either mode, the first four bytes do not contain valid data. These should be discarded.

9. Continue reading eye monitor data until you have read the entire 64 X 64 array.

10. Clear bit 7 of register 0x24. This disables fast eye monitor mode.

11. Set bit 5 of register 0x11. This will return control of the eye monitor circuitry to the CDR state machine.

12. Set bit 7 of register 0x3e. This re-enables the HEO and VEO lock monitoring.

Enabling Slow Rise/Fall Time on the Output Driver

Normally the rise and fall times of the output driver of the DS125RT410 are set by the slew rate of the output

transistors. By default, the output transistors are biased to provide the maximum possible slew rate, and hence

the minimum possible rise and fall times. In some applications, slower rise and fall times may be desired. For

example, slower rise and fall times may reduce the amplitude of electromagnetic interference (EMI) produced by

a system.

Setting bit 2 of register 0x18 will adjust the output driver circuitry to increase the rise and fall times of the signal.

Setting this bit will approximately double the nominal rise and fall times of the DS125RT410 output driver. This bit

is cleared by default.

Inverting the Output Polarity

In some systems, the polarity of the data does not matter. In systems where it does matter, it is sometimes

necessary, for the purposes of trace routing, for example, to invert the normal polarities of the data signals.

The DS125RT410 can invert the polarity of the data signals by means of a register write. Writing a 1 to bit 7 of

register 0x1f inverts the polarity of the output signal for the selected channel. This can provide additional flexibility

in system design and board layout.

Overriding the Figure of Merit for Adaptation

bits 7 and 6

The default figure of merit for both the CTLE adaptation in the DS125RT410 is simple. The horizontal and

vertical eye openings are measured for each CTLE boost setting. The vertical eye opening is scaled to a

constant reference vertical eye opening and the smaller of the horizontal or vertical eye opening is taken as the

figure of merit for that set of equalizer settings. The objective is to adapt the equalizer to a point where the

horizontal and vertical eye openings are both as large as possible. This usually provides optimum bit error rate

performance for most transmission channels.

In some systems the adaptation can reach a better setting if only the horizontal or only vertical eye opening is

used to compute the figure of merit rather than using both. This will be system-dependent and the user must

determine through experiment whether this provides better adaptation in the user's system. For the

DS125RT410, the CTLE figure of merit type can be set using register 0x31, bits 4:3. The value of this two-bit

field versus the configured figure of merit type is shown in Table 12.

0x0

0x1

0x2

Table 12. Figure of Merit Type Setting

Figure of Merit Type

Both HEO and VEO are used

Only HEO is used

Only VEO is used

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