DS125RT410 Datasheet, PDF (14/42 Pages) Texas Instruments – DS125RT410 Low Power Multi-Rate Quad Channel Retimer

DS125RT410
SNLS459 – APRIL 2011
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Note that for the entries in Table 2 where the divider ratios are the same for the two groups, the expected PPM
count for the two groups does not have to be the same. Therefore, in ref_mode 3, a single set of register settings
can be used to specify multiple VCO frequencies either with the same divider ratio or with different divider ratios.
Ref_mode 3 Mode (reference clock required)
Ref_mode 3 requires an external 25 MHz clock. This mode of operation is set in register 0x36 bits [5:4] = 2'b11
and is the default setting. In ref_mode 3, the external reference clock is used to aid initial phase lock, and to
determine when its VCO is properly phase-locked. An external oscillator should be used to generate a 2.5V, 25
MHz reference signal which is connected to the DS125RT410 on the reference clock input pin (pin 19). The
DS125RT410 does not include a crystal oscillator circuit, so a stand-alone external oscillator is required.
The reference clock speeds up the initial phase lock acquisition. The DS125RT410 is set to phase lock to a
known data rate, or a constrained set of known data rates, and the digital circuitry in the DS125RT410
preconfigures the VCO frequency. This enables the DS125RT410 phase-lock to the incoming signal very quickly.
The reference clock is used to calibrate the VCO coarse tuning. However, the reference clock is not synchronous
to the data stream, and the quality of the reference clock does not affect the jitter on the output retimed data. The
retimed data clock for each channel is synchronous to the VCO internal to that channel of the DS125RT410.
The phase noise of the reference clock is not critical. Any commercially-available 25 MHz oscillator can provide
an acceptable reference clock. The reference clock can be daisy-chained from one retimer to another so that
only one reference oscillator is required in a system.
False Lock Detector Setting
The register 0x2F, bit 1 is set to 1 by default, which disables the false lock detector. This bit must be set to 0 to
enable the false lock detector function.
Reference Clock In
REFCLK_IN pin 19 is for reference clock input. A 25 MHz oscillator should be connected to pin 19. See Electrical
Characteristics for the requirements on the 25 MHz clock. The frequency of the reference clock should always be
25 MHz no matter what data rate or mode of operation is used.
Reference Clock Out
REFCLK_OUT pin 42 is the reference clock output pin. The DS125RT410 drives a buffered replica of the 25
MHz reference clock input on this output pin. If there are multiple DS125RT410 in the system, the REFCLK_OUT
pin can be directly connected to the REFCLK_IN pin of another DS125RT410 in a daisy chain connection. The
other option is to connect the external 25 MHz oscillator to a clock fanout buffer to distribute the 25 MHz clock to
each DS125RT410, which ensures there is a reference clock for the DS125RT410.
Driver Output Voltage
The differential output voltage of the DS125RT410 can be configured from a nominal setting of 600 mV peak-to-
peak differential to a nominal setting of 1.3 V peak-to-peak differential, depending upon the application. The
driver output voltage as set is the typical peak-to-peak differential output voltage with no de-emphasis enabled.
Driver Output De-Emphasis
The output de-emphasis level of the DS125RT410 can be configured from a nominal setting of 0 dB to a nominal
setting of -15 dB depending upon the application. Larger absolute values of the de-emphasis setting provide
more pre-distortion of the output driver waveform, accentuating the high-frequency components of the output
driver waveform relative to the low-frequency components. Greater values of de-emphasis can compensate for
greater dispersion in the transmission media at the output of the DS125RT410. The output de-emphasis level as
set is the typical value to which the output signal will settle following the de-emphasis pulse interval in dB relative
to the output VOD.
Driver Output Rise/Fall Time
In some applications, a longer rise/fall time for the output signal is desired. This can reduce electromagnetic
interference (EMI) generated by fast switching waveforms. This is necessary in some applications for regulatory
compliance. In others, it can reduce the crosstalk in the system.
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