DS125RT410 Datasheet, PDF (27/42 Pages) Texas Instruments – DS125RT410 Low Power Multi-Rate Quad Channel Retimer

DS125RT410
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SNLS459 – APRIL 2011
channel register 0x01), then the controller might alert an operator or change the channel configuration. This
is system dependent.
8. Reading the interrupt status registers will clear the interrupt. if this does not cause the interrupt input to go
high, then another device on the same input has generated an interrupt. The controller can address the next
device using the procedure above.
9. Once all the interrupt registers for all channels for all DS125RT410s that generated interrupts have been
read, clearing all the interrupt indications, the INT line should go high again. This indicates that all the
existing interrupt conditions have been serviced.
The channel registers referred to above, registers 0x01, 0x30, 0x32, and 0x36, are described in the channel
registers table, Table 7.
Overriding the CTLE Boost Setting
Register 0x03, Register 0x13, bit 2, and Register 0x3a
To override the CTLE boost settings, register 0x03 is used. This register contains the currently-applied CTLE
boost settings. The boost values can be overridden by using the two-bit fields in this register as shown in the
table.
The final stage of the CTLE has an additional control bit which sets it to a limiting mode. For some channels, this
additional setting improves the bit error rate performance. This bit is bit 2 of register 0x13.
If the DS125RT410 loses lock because of a change in the CTLE settings, the DS125RT410 will initiate its lock
and adaptation sequence again. Thus, if you write new CTLE boost values to register 0x03 and 0x13 which
cause the DS125RT410 to drop out of lock, the DS125RT410 may, in the process of reacquiring the CDR lock,
reset the CTLE settings to different values than those you set in register 0x03 and 0x13. If this behavior is not
understood, it can appear that the DS125RT410 did not accept the values you wrote to the CTLE boost registers.
What's really happening, however, is that the lock and adaptation sequence is overriding the CTLE values you
wrote to the CTLE boost registers. This will not happen unless the DS125RT410 drops out of lock.
if the adapt mode is set to 0 (bits 6:5 of channel register 0x31), then the CTLE boost values will not be
overridden, but the DS125RT410 may still lose lock. If this happens, the DS125RT410 will attempt to reacquire
lock. if the reference mode is set appropriately, and if the rate/subrate code is set to permit it, the DS125RT410
will begin searching for CDR lock at the highest allowable VCO divider ratio – that is, at the lowest configured bit
rate. At this lowest bit rate, the CTLE boost settings used will come not from the values in register 0x03, and
0x13, but rather from register 0x3a, the fixed CTLE boost setting for lower data rates. This setting will be written
into boost setting register 0x03 during the lock search process. This value may be different from the value you
set in register 0x03, so, again, it may appear that the DS125RT410 has not accepted the CTLE boost settings
you set in registers 0x03 and 0x13. The interactions of the lock and adaptation sequences with the manually-set
CTLE boost settings can be difficult to understand.
To manually override the CTLE boost under all conditions, perform the following steps.
1. Set the DS125RT410 channel adapt mode to 0 by writing 0x0 to bits 6:5 of channel register 0x31.
2. Set the desired CTLE boost setting in register 0x3a. If the DS125RT410 loses lock and attempts to lock to a
lower data rate, it will use this CTLE boost setting.
3. Set the desired CTLE boost setting in register 0x03. This may cause the DS125RT410 to lose lock.
4. If desired, set the CTLE stage 3 limiting bit, bit 2 of register 0x13.
If the DS125RT410 loses lock when the CTLE boost settings are set according to the sequence above, the
DS125RT410 will try to reacquire lock, but it will not change the CTLE boost settings in order to do so.
Overriding the VCO Search Values
Register 0x08, bits 4:0, Register 0x09, bit 7, Register 0x0b, bits 4:0, Register 0x36, bits 5:4 and 2:0, and Register
0x2f, bits 7:6 and 5:4
Registers 0x08 and 0x0b contain CAP DAC override values. Normally, when bits 5:4 of register 0x36 are set to
2'b11, then the DS125RT410 performs an initial search to determine the correct CAP DAC setting (coarse VCO
tuning) for the selected rate and subrate. The rate and subrate settings (bits 7:6 and 5:4 of register 0x2f)
determine the frequency range to be searched, with the 25 MHz reference clock used as the frequency reference
for the frequency search.
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