THS1031IPW Datasheet, PDF (32/41 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
PRINCIPLES OF OPERATION
driving REFTF and REFBF (full external reference mode)
AVDD
REFTF
AGND
AVDD
To REFBS
(For Kelvin Connection)
680 Ω
REFBF
To REFTS
(For Kelvin Connection)
AGND
Figure 38. Equivalent Circuit of REFTF and REFBF Inputs
Note the need for off-chip decoupling.
clamp operation
The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or by
programming the on-chip clamp DAC.
clamp acquisition time
Figure 39 shows the basic operation of the clamp circuit with the analog input AIN coupled via an RC circuit.
CLAMPIN
10-Bit
DAC
CLAMP
Control Register
+
_
VCLAMP
CIN _RIN
AIN
SW1
VIN
S/H
Figure 39. Schematic of Clamp Circuitry
After powerup, the clamp circuit requires SW1 to be closed to charge the coupling capacitor, C_IN, to the voltage
required to set the dc clamp level at AIN. The charging time required to set the correct clamp voltage is called
+ ǒ Ǔ ^{the clamp acquisition time, tACQ:}
tACQ
CIN
RIN
In
Vc
Ve
(19)
Vc is the difference between the dc bias voltage level of the input signal, V_IN, and the target clamp output voltage,
V_(clamp). Ve is the difference between the ideal Vc and the actual Vc obtained during the acquisition time. The
maximum tolerable error depends on the application requirements.
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