THS1031IPW Datasheet, PDF (27/41 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
PRINCIPLES OF OPERATION
digital control registers
The THS1031 contains two clamp registers and a control register for user programming of THS1031 operation.
Binary data can be written into these registers by using pins I/O0 to I/O9 and the WR and OE pins (see the
previous section). In input mode, the two I/O bus MSBs are address bits, 00 addressing clamp register 1, 01
clamp register 2, and 10 the control register.
ADDRESS
I/O[9:8]
00
01
10
11
DESCRIPTION
Clamp Reg. 1
Clamp Reg. 2
Control Reg.
Reserved
DEF
(HEX)
00
00
01
Table 3. Register Map
B7
DAC[7]
B6
DAC[6]
CLDIS
B5
DAC[5]
TWOC
BIT
B4
B3
DAC[4] DAC[3]
CLINT PDWN
B2
DAC[2]
PGA[2]
B1
DAC[1]
DAC[9]
PGA[1]
B0
DAC[0]
DAC[8]
PGA[0]
REGISTER
Control Register
I/O[9:8] = 10
Clamp Register 1
I/O[9:8] = 00
Clamp Register 2
I/O[9:8] = 01
Table 4. Register Contents
BIT NO BIT NAME(S)
2:0
PGA[2:0]
3
PDWN
4
CLINT
5
TWOC
6
CLDIS
7
7:0
DAC[7:0]
7:2
1:0
DAC[9:8]
DEFAULT
0
0
0
0
0
0
0
DESCRIPTION
PGA gain:
000 = 0.5
001 = 1.0 (default value)
010 = 1.5
011 = 2.0
100 = 2.5
101 = 3.0
110 = 3.5
111 = 4.0
Power down
0 = THS1031 powered up
1 = THS1031 powered down
Clamp voltage internal/external
0 = external analog clamp voltage from CLAMPIN pin
1 = from onboard DAC (see clamp register)
Output format
0 = unsigned binary
1 = two’s complement
Clamp amplifier disable (for power saving)
0 = Enable
1 = Disable
Unused
Clamp DAC voltage
(DAC[0] = LSB.)
DAC[9:0] = 00h: Clamp voltage = REFBF
DAC[9:0] = 3Fh: Clamp voltage = REFTF
Unused
Clamp DAC voltage
(DAC[9] = MSB)
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