THS1031IPW Datasheet, PDF (22/41 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
+
VBG
+
_
_
Internal
Reference
Buffer
Mode =
AVDD
2
VREF = External
REFSENSE
AVDD
AGND
Figure 23. Drive VREF Mode
operating configuration examples
This section provides examples of operating configurations.
Figure 24 shows the operating configuration in top/bottom mode for a 2-V span single-ended input, using VREF
to drive REFTS and with PGA gain = 1. Connecting the MODE pin to AV_DD puts the THS1031 in top/bottom
mode. Connecting pin REFSENSE to AGND sets the output of the ORG to 2 V. REFTS and REFBS are
user-connected to VREF and AGND respectively to match the AIN pin input range to the voltage range of the
input signal.
AVDD
2V
1V
AIN
MODE
0V
VREF = 2 V
0.1 µF
0.1 µF
REFTS
10 µF
REFTF
REFSENSE
0.1 µF
REFBF
REFBS
Figure 24. Operation Configuration in Top/Bottom Mode
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