THS1031IPW Datasheet, PDF (31/41 Pages) Texas Instruments – 3-V TO 5.5-V, 10-BIT, 30 MSPS CMOS ANALOG-TO-DIGITAL CONVERTER

THS1031
3-V TO 5.5-V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002
PRINCIPLES OF OPERATION
driving the internal reference buffer (top/bottom mode)
Figure 36 shows the load present on the REFTS and REFBS pins in top/bottom mode due to the internal
reference buffer only. The sample and hold must also be driven via these pins, which adds additional load.
AVDD
REFTS
REFBS
RIN
14 kΩ
AVDD
Mode = ₂
AGND
+
AVDD + REFTS + REFBS _
4
Figure 36. Equivalent Circuit of Inputs to Internal Reference Buffer
Equations for the currents flowing into REFTS and REFBS are:
+ ⁽³
IINTS
* * REFTS AVDD REFBS)
(4 RIN)
(18)
+ ⁽³
IINBS
* * REFBS AVDD REFTS)
(4 RIN)
These currents must be provided by the sources on REFTS and REFBS in addition to the requirements of driving
the sample and hold. Tolerance on these currents are ±50%.
driving REFTS and REFBS
AVDD
REFTS
REFBS
CLK
C1
7 pF
0.6 pF
C2 ^CSAMPLE
0.6 pF
AGND
Mode = AVDD
Internal
Reference
Buffer
CLK
+
_ _VLAST
Figure 37. Equivalent Circuit of REFTS and REFBS Inputs
This is essentially a combination of driving the ADC internal reference buffer (if in top/bottom mode) and also
driving a switched capacitor load like AIN, but with the sampling capacitor and C_P2 on each pin now being 0.6 pF
and about 0.6 pF respectively.
• POST OFFICE BOX 655303 DALLAS, TEXAS 75265
31